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strix/fpga
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randogoth 504b00752a feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)
2026-10-25 13:03:53 +02:00
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rtl feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2) 2026-10-25 13:03:53 +02:00
sim feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2) 2026-10-25 13:03:53 +02:00
src feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2) 2026-10-25 13:03:53 +02:00