randogoth
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504b00752a
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feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)
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2026-10-25 13:03:53 +02:00 |
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randogoth
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0332d8eb33
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feat: add FPGA raw jitter capture design with SPI register interface
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2026-10-25 12:25:25 +02:00 |
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randogoth
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3ee8a5c3db
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chore: add Quartus Prime Lite toolchain via nix flake in devbox
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2026-10-25 12:09:56 +02:00 |
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randogoth
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309b836af0
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chore: add devbox setup and ignore Quartus build files
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2026-10-25 11:56:34 +02:00 |
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randogoth
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833d86f15e
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fpga project set up
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2024-07-21 18:38:16 +03:00 |
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randogoth
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816ae0fc75
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init
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2024-07-21 18:19:27 +03:00 |
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