randogoth 504b00752a feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)		2026-10-25 13:03:53 +02:00
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freq_counter.v	feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)	2026-10-25 13:03:53 +02:00
raw_capture.v	feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)	2026-10-25 13:03:53 +02:00
ring_bank.v	feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)	2026-10-25 13:03:53 +02:00
ring_osc.v	feat: add FPGA raw jitter capture design with SPI register interface	2026-10-25 12:25:25 +02:00
spi_slave.v	feat: add FPGA raw jitter capture design with SPI register interface	2026-10-25 12:25:25 +02:00
strix.v	feat: add FPGA raw jitter capture design with SPI register interface	2026-10-25 12:25:25 +02:00
strix_core.v	feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)	2026-10-25 13:03:53 +02:00
sys_pll.v	feat: add FPGA raw jitter capture design with SPI register interface	2026-10-25 12:25:25 +02:00