34 lines
1.2 KiB
Verilog
34 lines
1.2 KiB
Verilog
// One generator: two rings of different lengths whose enhanced outputs are XORed, plus
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// the intermediate signals exposed for jitter characterization. All four are sampled
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// every clock.
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module entropy_gen #(
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parameter LENGTH_A = 12,
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parameter LENGTH_B = 10
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) (
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input wire clk,
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input wire enable,
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output wire [3:0] samples // {pair XOR, enhanced B, enhanced A, single tap of A}
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);
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wire ring_a_tap, ring_a_enhanced, ring_b_tap, ring_b_enhanced;
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ring_osc #(.LENGTH(LENGTH_A)) ring_a (
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.enable(enable), .first_tap(ring_a_tap), .enhanced(ring_a_enhanced)
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);
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ring_osc #(.LENGTH(LENGTH_B)) ring_b (
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.enable(enable), .first_tap(ring_b_tap), .enhanced(ring_b_enhanced)
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);
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(* keep *) wire pair_xor = ring_a_enhanced ^ ring_b_enhanced;
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// sample_raw catches the asynchronous ring signals and may go metastable;
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// sample_sync resolves it. The SDC file cuts timing into sample_raw.
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reg [3:0] sample_raw, sample_sync;
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always @(posedge clk) begin
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sample_raw <= {pair_xor, ring_b_enhanced, ring_a_enhanced, ring_a_tap};
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sample_sync <= sample_raw;
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end
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assign samples = sample_sync;
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endmodule
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