// One generator: two rings of different lengths whose enhanced outputs are XORed, plus
// the intermediate signals exposed for jitter characterization. All four are sampled
// every clock.
module entropy_gen #(
    parameter LENGTH_A = 12,
    parameter LENGTH_B = 10
) (
    input  wire       clk,
    input  wire       enable,
    output wire [3:0] samples   // {pair XOR, enhanced B, enhanced A, single tap of A}
);

    wire ring_a_tap, ring_a_enhanced, ring_b_tap, ring_b_enhanced;

    ring_osc #(.LENGTH(LENGTH_A)) ring_a (
        .enable(enable), .first_tap(ring_a_tap), .enhanced(ring_a_enhanced)
    );
    ring_osc #(.LENGTH(LENGTH_B)) ring_b (
        .enable(enable), .first_tap(ring_b_tap), .enhanced(ring_b_enhanced)
    );

    (* keep *) wire pair_xor = ring_a_enhanced ^ ring_b_enhanced;

    // sample_raw catches the asynchronous ring signals and may go metastable;
    // sample_sync resolves it. The SDC file cuts timing into sample_raw.
    reg [3:0] sample_raw, sample_sync;
    always @(posedge clk) begin
        sample_raw  <= {pair_xor, ring_b_enhanced, ring_a_enhanced, ring_a_tap};
        sample_sync <= sample_raw;
    end

    assign samples = sample_sync;

endmodule