50 lines
2.8 KiB
Markdown
50 lines
2.8 KiB
Markdown
# STRIX
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### Satellite True Random Information eXtractor
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A portable wireless True Random Number Generator built on an Arduino MKR Vidor 4000.
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## Design
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Entropy comes from FPGA ring oscillators whose sampled timing jitter is XOR-combined into output bits, with no pseudo-random post-processing. A SAMD21 serves the results over USB (WiFi is planned).
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- 4 independent generators × 90 ring oscillators. Each generator XORs its rings every 120 MHz clock (spatial) and then several consecutive bits (temporal, default 5): about 24 Mbps per generator.
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- Separate stream per generator, plus a combined stream of all healthy generators
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- On-device health tests per generator: NIST SP 800-90B repetition count and adaptive proportion, plus a dead-ring monitor
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- Live statistics per trial: bias, z-score, random walk and lag-1 autocorrelation, with rolling and cumulative windows
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- Configurable random-walk / majority-vote bias amplifier on a bias path and an autocorrelation path, with sub-trial voting
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- Von Neumann extractor that can be toggled on the stream, statistics and amplifier paths
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- Raw ring captures and frequency measurement for characterization
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The USB protocol is documented in [arduino/strix/API.md](arduino/strix/API.md).
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## Layout
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- `fpga/rtl/`: Verilog sources; `fpga/sim/`: testbenches; `fpga/src/`: Quartus project
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- `arduino/strix/`: device firmware
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- `arduino/strix_capture/`: characterization tool firmware, used by `tools/jitter.py`
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- `arduino/libraries/`: `StrixFPGA` (FPGA boot, SPI access, embedded FPGA image) and `VidorBoot` (vendored subset of Arduino's VidorPeripherals)
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- `tools/`: FPGA image converter, jitter and statistics experiments, API check
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## Development (Linux)
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The toolchain is managed by [devbox](https://www.jetify.com/devbox): `arduino-cli`, Intel Quartus Prime Lite (Cyclone 10 LP only, through a Nix flake in `nix/`), Icarus Verilog, Python and Rust.
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1. `devbox run setup`: install the Arduino SAMD core and libraries
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2. `devbox run sim`: run the FPGA testbenches
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3. `devbox run fpga`: build the FPGA bitstream (about 10 minutes)
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4. `devbox run image`: embed the bitstream in the `StrixFPGA` library
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5. `devbox run build`, then `devbox run upload`: build and flash the firmware (`PORT` defaults to `/dev/ttyACM0`)
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6. `devbox run api-check`: end-to-end check of the USB API
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Serial access requires membership in the `dialout` group. For characterization, flash the capture tool with `devbox run upload-capture` and use `devbox run jitter <freq|rings|sweep|output|health|stats|amp|pairs>`. `devbox run onod-build` builds the onod3000 test suite used by `jitter output` and `api-check`.
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## TODO
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- Serve randomness over WiFi (NINA pass-through in the FPGA is wired, firmware not yet)
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- Make Vidor pairable via Bluetooth
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- Battery pack
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- 3D case
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---
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## [Development Notes](NOTES.md)
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