4 commits

Author	SHA1	Message	Date
randogoth	d51a6c0ca8	feat: add capture sketch, Vidor image tool and jitter analysis script	2026-10-25 12:30:16 +02:00
randogoth	0332d8eb33	feat: add FPGA raw jitter capture design with SPI register interface	2026-10-25 12:25:25 +02:00
randogoth	3ee8a5c3db	chore: add Quartus Prime Lite toolchain via nix flake in devbox	2026-10-25 12:09:56 +02:00
randogoth	309b836af0	chore: add devbox setup and ignore Quartus build files	2026-10-25 11:56:34 +02:00