feat: add FPGA raw jitter capture design with SPI register interface

devbox.json

@@ -1,6 +1,13 @@
 {
-  "$schema":  "https://raw.githubusercontent.com/jetify-com/devbox/0.17.2/.schema/devbox.schema.json",
-  "packages": ["arduino-cli@latest", "path:./nix#quartus"],
+  "$schema": "https://raw.githubusercontent.com/jetify-com/devbox/0.17.2/.schema/devbox.schema.json",
+  "packages": [
+    "arduino-cli@latest",
+    "path:./nix#quartus",
+    "python312@latest",
+    "python312Packages.pyserial@latest",
+    "python312Packages.numpy@latest",
+    "iverilog@latest"
+  ],
   "shell": {
     "init_hook": [
       "echo 'Welcome to devbox!' > /dev/null"
@@ -14,6 +21,11 @@
       "build": [
         "arduino-cli compile --fqbn arduino:samd:mkrvidor4000 arduino/strix"
       ],
+      "sim": [
+        "mkdir -p /tmp/strix-sim",
+        "iverilog -g2005 -DSIM -o /tmp/strix-sim/tb_strix_core fpga/sim/tb_strix_core.v fpga/rtl/strix_core.v fpga/rtl/entropy_gen.v fpga/rtl/ring_osc.v fpga/rtl/raw_capture.v fpga/rtl/spi_slave.v",
+        "vvp -n /tmp/strix-sim/tb_strix_core"
+      ],
       "fpga": [
         "cd fpga/src && quartus_sh --flow compile strix"
       ]