Commit graph

14 commits

Author SHA1 Message Date
randogoth
6bee626b7f feat: add per-second GCP-format trials with history, watch and HTTP access (FPGA v10) 2026-10-25 18:23:21 +02:00
randogoth
5c69d826a2 fix: hand GPIO0 to the WiFi module, count only healthy generators, shorten amplifier stage path (FPGA v9) 2026-10-25 17:48:20 +02:00
randogoth
853addaa22 feat: hold the WiFi module in reset until enabled by the firmware (FPGA v8) 2026-10-25 16:13:41 +02:00
randogoth
7777384495 feat: add entropy byte stream FIFO and faster SPI read-back (FPGA v7) 2026-10-25 15:29:36 +02:00
randogoth
8541cce59c feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6) 2026-10-25 14:59:27 +02:00
randogoth
5305d66102 feat: add live statistics with per-trial snapshots and von Neumann option (FPGA v5) 2026-10-25 14:27:45 +02:00
randogoth
67bd7eec58 feat: add per-generator NIST health tests and dead-ring monitor, onod3000 output test (FPGA v4) 2026-10-25 13:36:55 +02:00
randogoth
585e755c66 feat: add four 90-ring entropy generators with spatial and temporal XOR (FPGA v3) 2026-10-25 13:23:27 +02:00
randogoth
504b00752a feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2) 2026-10-25 13:03:53 +02:00
randogoth
0332d8eb33 feat: add FPGA raw jitter capture design with SPI register interface 2026-10-25 12:25:25 +02:00
randogoth
3ee8a5c3db chore: add Quartus Prime Lite toolchain via nix flake in devbox 2026-10-25 12:09:56 +02:00
randogoth
309b836af0 chore: add devbox setup and ignore Quartus build files 2026-10-25 11:56:34 +02:00
randogoth
833d86f15e fpga project set up 2024-07-21 18:38:16 +03:00
randogoth
816ae0fc75 init 2024-07-21 18:19:27 +03:00