85 lines
2.8 KiB
Verilog
85 lines
2.8 KiB
Verilog
// STRIX top level for the Arduino MKR Vidor 4000. Port names match the Vidor constraints
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// in strix.qsf; unused board pins are left out and stay tri-stated.
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module strix (
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input wire iCLK, // 48 MHz from the SAMD21 (GCLK0)
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inout wire [14:0] bMKR_D, // header D0-D14, shared with the SAMD21
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inout wire [6:0] bMKR_A, // header A0-A6, shared with the SAMD21
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// NINA-W102 WiFi module
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inout wire bWM_PIO1, // NINA MISO
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inout wire bWM_PIO7, // NINA ACK (GPIO33)
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inout wire bWM_PIO27, // NINA GPIO0
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inout wire bWM_PIO28, // NINA SS (GPIO5)
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inout wire bWM_PIO29, // NINA SCK
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inout wire bWM_PIO36, // NINA MOSI
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input wire iWM_TX,
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inout wire oWM_RX,
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inout wire oWM_RESET,
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output wire oSAM_INT // interrupt line to the SAMD21
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);
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// Clock and reset
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wire clk, pll_locked;
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sys_pll pll (.inclk0(iCLK), .c0(clk), .locked(pll_locked));
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reg [2:0] reset_pipe = 3'b111;
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always @(posedge clk or negedge pll_locked)
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if (!pll_locked) reset_pipe <= 3'b111;
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else reset_pipe <= {reset_pipe[1:0], 1'b0};
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wire reset = reset_pipe[2];
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// NINA pass-through: the SAMD21 talks to the WiFi module as if wired directly.
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wire sam_nina_mosi = bMKR_D[8]; // SERCOM1
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wire sam_nina_sck = bMKR_D[9];
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wire sam_nina_ss = bMKR_D[5];
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wire sam_nina_gpio0 = bMKR_D[6];
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wire sam_nina_resetn = bMKR_D[7];
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wire sam_uart_tx = bMKR_D[14];
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assign bWM_PIO36 = sam_nina_mosi;
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assign bWM_PIO29 = sam_nina_sck;
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assign bWM_PIO28 = sam_nina_ss;
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assign bWM_PIO27 = sam_nina_gpio0;
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assign oWM_RESET = sam_nina_resetn;
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assign oWM_RX = sam_uart_tx;
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assign bWM_PIO1 = 1'bz; // inputs from NINA
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assign bWM_PIO7 = 1'bz;
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wire nina_miso = bWM_PIO1; // to D10
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wire nina_ack = bWM_PIO7; // to D4
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wire nina_uart_tx = iWM_TX; // to D13
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// STRIX SPI link on SAMD21 SERCOM0 alternate pins: A3 MOSI, A4 SCK, A5 SS, A6 MISO.
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wire strix_mosi = bMKR_A[3];
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wire strix_sck = bMKR_A[4];
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wire strix_ss_n = bMKR_A[5];
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wire strix_miso, capture_done;
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strix_core core (
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.clk(clk), .reset(reset),
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.spi_sck(strix_sck), .spi_mosi(strix_mosi), .spi_ss_n(strix_ss_n),
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.spi_miso(strix_miso), .capture_done(capture_done)
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);
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assign oSAM_INT = capture_done;
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// Header pins driven by the FPGA; all others are inputs.
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genvar d;
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generate
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for (d = 0; d < 15; d = d + 1) begin : header_d
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assign bMKR_D[d] = (d == 4) ? nina_ack :
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(d == 10) ? nina_miso :
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(d == 13) ? nina_uart_tx : 1'bz;
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end
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endgenerate
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assign bMKR_A = {strix_miso, 6'bzzzzzz};
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endmodule
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