130 lines
4.9 KiB
Verilog
130 lines
4.9 KiB
Verilog
// Board-independent STRIX logic: entropy generator, raw capture and the SPI register
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// interface to the SAMD21.
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//
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// SPI protocol (mode 0, one transaction per ss_n low period): the first byte is a command,
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// bit 7 = read (1) or write (0), bits 6:0 = register address. A write stores the following
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// byte(s) in that register. A read returns the register in every following byte; DATA
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// advances through the capture buffer with each byte, continuing across transactions.
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module strix_core #(
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parameter CAPTURE_ADDR_WIDTH = 15
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) (
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input wire clk,
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input wire reset,
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input wire spi_sck,
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input wire spi_mosi,
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input wire spi_ss_n,
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output wire spi_miso,
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output wire capture_done
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);
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localparam [7:0] VERSION = 8'h01;
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localparam [6:0] REG_ID0 = 7'h00, // "STRX"
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REG_ID1 = 7'h01,
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REG_ID2 = 7'h02,
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REG_ID3 = 7'h03,
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REG_VERSION = 7'h04,
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REG_SOURCE = 7'h08, // 0 tap A, 1 enhanced A, 2 enhanced B, 3 pair
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REG_DECIM_HIGH = 7'h09,
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REG_DECIM_LOW = 7'h0A,
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REG_CONTROL = 7'h0B, // write: bit 0 start capture, bit 1 rewind DATA
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REG_STATUS = 7'h0C, // bit 0 busy, bit 1 done
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REG_DATA = 7'h10;
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// Entropy and capture
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wire [3:0] samples;
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entropy_gen generator (.clk(clk), .enable(1'b1), .samples(samples));
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reg [1:0] source;
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reg [15:0] decimation;
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reg capture_start;
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wire capture_busy;
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reg [CAPTURE_ADDR_WIDTH-1:0] prefetch_addr;
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wire [7:0] capture_byte;
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raw_capture #(.ADDR_WIDTH(CAPTURE_ADDR_WIDTH)) capture (
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.clk(clk), .reset(reset), .samples(samples), .source(source),
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.decimation(decimation), .start(capture_start),
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.busy(capture_busy), .done(capture_done),
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.read_addr(prefetch_addr), .read_data(capture_byte)
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);
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// SPI
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wire selected, rx_valid, rx_is_first, tx_loaded;
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wire [7:0] rx_byte;
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reg [7:0] tx_byte;
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spi_slave spi (
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.clk(clk), .reset(reset),
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.sck(spi_sck), .mosi(spi_mosi), .ss_n(spi_ss_n), .miso(spi_miso),
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.selected(selected), .rx_valid(rx_valid), .rx_byte(rx_byte),
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.rx_is_first(rx_is_first), .tx_byte(tx_byte), .tx_loaded(tx_loaded)
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);
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reg is_read;
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reg [6:0] reg_addr;
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// DATA bytes are prefetched one ahead: prefetch_addr moves when a byte is loaded for
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// shifting, bytes_read only when it has been fully clocked out. Between transactions
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// prefetch_addr rewinds to bytes_read so the trailing prefetch is not lost.
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reg [CAPTURE_ADDR_WIDTH-1:0] bytes_read;
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wire reading_data = is_read && reg_addr == REG_DATA;
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always @(*) begin
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case (reg_addr)
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REG_ID0: tx_byte = "S";
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REG_ID1: tx_byte = "T";
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REG_ID2: tx_byte = "R";
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REG_ID3: tx_byte = "X";
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REG_VERSION: tx_byte = VERSION;
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REG_SOURCE: tx_byte = {6'd0, source};
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REG_DECIM_HIGH: tx_byte = decimation[15:8];
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REG_DECIM_LOW: tx_byte = decimation[7:0];
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REG_STATUS: tx_byte = {6'd0, capture_done, capture_busy};
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REG_DATA: tx_byte = capture_byte;
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default: tx_byte = 8'h00;
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endcase
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end
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always @(posedge clk) begin
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capture_start <= 1'b0;
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if (reset) begin
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source <= 2'd3;
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decimation <= 16'd1;
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is_read <= 1'b0;
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reg_addr <= 7'd0;
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bytes_read <= {CAPTURE_ADDR_WIDTH{1'b0}};
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prefetch_addr <= {CAPTURE_ADDR_WIDTH{1'b0}};
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end else begin
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if (!selected)
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prefetch_addr <= bytes_read;
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else if (tx_loaded && reading_data)
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prefetch_addr <= prefetch_addr + 1'b1;
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if (rx_valid) begin
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if (rx_is_first) begin
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is_read <= rx_byte[7];
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reg_addr <= rx_byte[6:0];
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end else if (reading_data) begin
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bytes_read <= bytes_read + 1'b1;
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end else if (!is_read) begin
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case (reg_addr)
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REG_SOURCE: source <= rx_byte[1:0];
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REG_DECIM_HIGH: decimation[15:8] <= rx_byte;
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REG_DECIM_LOW: decimation[7:0] <= rx_byte;
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REG_CONTROL: begin
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if (rx_byte[0]) capture_start <= 1'b1;
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if (rx_byte[0] || rx_byte[1]) bytes_read <= {CAPTURE_ADDR_WIDTH{1'b0}};
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end
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default: ;
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endcase
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end
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end
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end
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end
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endmodule
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