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amp_path.v
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feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)
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2026-10-25 14:59:27 +02:00 |
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amp_stage.v
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feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)
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2026-10-25 14:59:27 +02:00 |
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bias_amplifier.v
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feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)
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2026-10-25 14:59:27 +02:00 |
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entropy_generator.v
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feat: add live statistics with per-trial snapshots and von Neumann option (FPGA v5)
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2026-10-25 14:27:45 +02:00 |
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freq_counter.v
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feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)
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2026-10-25 13:03:53 +02:00 |
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health_monitor.v
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feat: add per-generator NIST health tests and dead-ring monitor, onod3000 output test (FPGA v4)
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2026-10-25 13:36:55 +02:00 |
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raw_capture.v
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feat: add four 90-ring entropy generators with spatial and temporal XOR (FPGA v3)
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2026-10-25 13:23:27 +02:00 |
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ring_osc.v
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feat: add FPGA raw jitter capture design with SPI register interface
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2026-10-25 12:25:25 +02:00 |
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spi_slave.v
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feat: add FPGA raw jitter capture design with SPI register interface
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2026-10-25 12:25:25 +02:00 |
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stats_block.v
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feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)
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2026-10-25 14:59:27 +02:00 |
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strix.v
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feat: add FPGA raw jitter capture design with SPI register interface
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2026-10-25 12:25:25 +02:00 |
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strix_core.v
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feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)
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2026-10-25 14:59:27 +02:00 |
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sys_pll.v
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feat: add FPGA raw jitter capture design with SPI register interface
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2026-10-25 12:25:25 +02:00 |
