348 lines
16 KiB
Verilog
348 lines
16 KiB
Verilog
// Board-independent STRIX logic: entropy generators with health monitors, live statistics,
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// source selection, raw capture, frequency counter and the SPI register interface to the SAMD21.
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//
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// SPI protocol (mode 0, one transaction per ss_n low period): the first byte is a command,
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// bit 7 = read (1) or write (0), bits 6:0 = register address. A write stores the following
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// byte(s) in that register. A read returns the register in every following byte; DATA
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// advances through the capture buffer with each byte, continuing across transactions.
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//
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// Capture sources, for generator g = 0..3:
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// 0x00+g processed output (spatial XOR, then temporal XOR; capture with decimation = TEMPORAL)
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// 0x04+g spatial XOR of all rings, every clock
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// 0x08+g enhanced output of ring RING_SELECT
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// 0x0C+g single tap of ring RING_SELECT
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//
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// Health: a generator is healthy when it is enabled, its monitor has completed a dead-ring
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// sweep, neither NIST test has failed since the last clear, and at most MAX_DEAD_RINGS rings
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// are dead. Per-generator registers at 0x30 + 4g: FLAGS, RCT_EVENTS, APT_EVENTS, DEAD_RINGS.
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//
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// Statistics channels 0-3 are the generators' processed outputs, channel 4 is the XOR of the
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// healthy generators' outputs. Reading STATS returns the latest trial snapshot (layout in
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// stats_block.v) byte by byte, starting at byte 0 in every transaction.
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module strix_core #(
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parameter CAPTURE_ADDR_WIDTH = 15,
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parameter FREQ_GATE_BITS = 24,
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parameter RINGS_PER_GEN = 90,
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parameter DEAD_WINDOW_BITS = 16,
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parameter TICK_CYCLES = 120000 // clk cycles per millisecond
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) (
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input wire clk,
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input wire reset,
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input wire spi_sck,
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input wire spi_mosi,
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input wire spi_ss_n,
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output wire spi_miso,
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output wire capture_done
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);
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localparam [7:0] VERSION = 8'h05;
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localparam GENERATORS = 4;
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localparam [6:0] REG_ID0 = 7'h00, // "STRX"
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REG_ID1 = 7'h01,
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REG_ID2 = 7'h02,
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REG_ID3 = 7'h03,
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REG_VERSION = 7'h04,
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REG_FREQ_GATE = 7'h05, // read-only: gate is 2^value clk cycles
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REG_GENERATORS = 7'h06, // read-only
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REG_RINGS = 7'h07, // read-only: rings per generator
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REG_SOURCE_A = 7'h08,
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REG_DECIM_HIGH = 7'h09,
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REG_DECIM_LOW = 7'h0A,
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REG_CONTROL = 7'h0B, // write: bit 0 start capture, bit 1 rewind DATA,
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// bit 2 start frequency measurement
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REG_STATUS = 7'h0C, // bit 0 capture busy, bit 1 capture done,
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// bit 2 frequency busy, bit 3 frequency valid
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REG_SOURCE_B = 7'h0D,
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REG_MODE = 7'h0E, // bit 0 pair capture (A and B per sample)
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REG_DATA = 7'h10,
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REG_RING_SELECT = 7'h11, // ring for the characterization sources and frequency
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REG_FREQ_COUNT3 = 7'h12, // prescaled edge count, most significant byte first
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REG_FREQ_COUNT2 = 7'h13,
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REG_FREQ_COUNT1 = 7'h14,
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REG_FREQ_COUNT0 = 7'h15,
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REG_GEN_ENABLE = 7'h16, // bit g enables generator g
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REG_TEMPORAL = 7'h17, // consecutive bits XORed per output bit, 1-8
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REG_FREQ_GEN = 7'h18, // generator for the frequency measurement
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REG_HEALTHY = 7'h20, // read-only: bit g = generator g healthy
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REG_HEALTH_CTRL = 7'h21, // write: bit 0 clears failures and event counters
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REG_RCT_CUTOFF = 7'h22, // repetition count test cutoff (run length)
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REG_APT_HIGH = 7'h23, // adaptive proportion test cutoff (per 1024 bits)
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REG_APT_LOW = 7'h24,
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REG_MAX_DEAD = 7'h25, // dead rings tolerated per generator
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REG_TRIAL_HIGH = 7'h26, // trial length in ms
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REG_TRIAL_LOW = 7'h27,
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REG_STATS_CTRL = 7'h28, // bit 0 von Neumann on the statistics path;
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// write bit 1: restart trials, sequence 0
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REG_STATS = 7'h40; // burst read of the trial snapshot
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// Per-generator health registers at 0x30 + 4g + index
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localparam [1:0] GEN_FLAGS = 2'd0, // bit 0 RCT failed, 1 APT failed, 2 too many dead rings,
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// 3 active, 4 sweep done, 5 healthy
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GEN_RCT_EVENTS = 2'd1,
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GEN_APT_EVENTS = 2'd2,
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GEN_DEAD_RINGS = 2'd3;
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// Generators
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reg [GENERATORS-1:0] gen_enable;
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reg [3:0] temporal;
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reg [7:0] ring_select;
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wire [GENERATORS-1:0] out_bit, out_valid, spatial_bit, ring_enhanced, ring_tap, ring_raw_tap;
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reg health_clear;
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reg [7:0] rct_cutoff, max_dead;
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reg [10:0] apt_cutoff;
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wire [GENERATORS-1:0] rct_failed, apt_failed, sweep_done, too_many_dead, healthy;
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wire [7:0] rct_events [0:GENERATORS-1];
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wire [7:0] apt_events [0:GENERATORS-1];
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wire [7:0] dead_rings [0:GENERATORS-1];
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genvar g;
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generate
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for (g = 0; g < GENERATORS; g = g + 1) begin : gen
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wire [RINGS_PER_GEN-1:0] ring_samples;
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wire active = gen_enable[g] && !reset;
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entropy_generator #(.RINGS(RINGS_PER_GEN)) generator (
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.clk(clk), .enable(gen_enable[g]), .temporal(temporal), .ring_select(ring_select),
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.out_bit(out_bit[g]), .out_valid(out_valid[g]), .spatial_bit(spatial_bit[g]),
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.ring_enhanced(ring_enhanced[g]), .ring_tap(ring_tap[g]),
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.ring_raw_tap(ring_raw_tap[g]), .ring_samples(ring_samples)
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);
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health_monitor #(.RINGS(RINGS_PER_GEN), .DEAD_WINDOW_BITS(DEAD_WINDOW_BITS)) monitor (
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.clk(clk), .active(active), .clear(health_clear),
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.sample_bit(spatial_bit[g]), .ring_samples(ring_samples),
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.rct_cutoff(rct_cutoff), .apt_cutoff(apt_cutoff),
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.rct_failed(rct_failed[g]), .apt_failed(apt_failed[g]),
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.rct_events(rct_events[g]), .apt_events(apt_events[g]),
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.dead_rings(dead_rings[g]), .sweep_done(sweep_done[g])
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);
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assign too_many_dead[g] = sweep_done[g] && dead_rings[g] > max_dead;
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assign healthy[g] = active && sweep_done[g] && !rct_failed[g] && !apt_failed[g]
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&& !too_many_dead[g];
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end
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endgenerate
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// Statistics. All generators share the temporal setting and run in lockstep, so
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// generator 0's valid strobe times every channel.
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reg [15:0] trial_ms;
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reg stats_von_neumann, stats_restart;
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reg [7:0] stats_index;
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wire [7:0] stats_byte;
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wire trial_end;
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// Registered inputs keep the health logic and the combining XOR off the counter paths;
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// every channel is delayed by the same cycle, so they stay aligned.
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reg [GENERATORS:0] stats_bits;
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reg stats_valid;
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reg [GENERATORS-1:0] stats_healthy;
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always @(posedge clk) begin
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stats_healthy <= healthy;
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stats_bits <= {^(out_bit & healthy), out_bit};
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stats_valid <= out_valid[0];
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end
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stats_block #(.CHANNELS(GENERATORS + 1), .TICK_CYCLES(TICK_CYCLES)) stats (
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.clk(clk), .reset(reset), .bits(stats_bits), .valid(stats_valid),
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.von_neumann(stats_von_neumann), .trial_ms(trial_ms), .restart(stats_restart),
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.healthy(stats_healthy), .read_index(stats_index), .read_byte(stats_byte),
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.trial_end(trial_end)
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);
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// Source selection
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reg [3:0] source_a, source_b;
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reg bit_a, bit_b;
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wire [15:0] all_sources = {ring_tap, ring_enhanced, spatial_bit, out_bit};
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always @(posedge clk) begin
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bit_a <= all_sources[source_a];
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bit_b <= all_sources[source_b];
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end
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// Capture
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reg pair_mode;
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reg [15:0] decimation;
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reg capture_start;
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wire capture_busy;
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reg [CAPTURE_ADDR_WIDTH-1:0] prefetch_addr;
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wire [7:0] capture_byte;
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raw_capture #(.ADDR_WIDTH(CAPTURE_ADDR_WIDTH)) capture (
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.clk(clk), .reset(reset), .bit_a(bit_a), .bit_b(bit_b), .pair_mode(pair_mode),
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.decimation(decimation), .start(capture_start),
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.busy(capture_busy), .done(capture_done),
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.read_addr(prefetch_addr), .read_data(capture_byte)
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);
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// Frequency counter
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reg [1:0] freq_gen;
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reg freq_start;
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wire freq_busy, freq_valid;
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wire [31:0] freq_count;
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freq_counter #(.GATE_BITS(FREQ_GATE_BITS)) counter (
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.clk(clk), .reset(reset), .signal(ring_raw_tap[freq_gen]), .start(freq_start),
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.busy(freq_busy), .valid(freq_valid), .count(freq_count)
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);
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// SPI
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wire selected, rx_valid, rx_is_first, tx_loaded;
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wire [7:0] rx_byte;
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reg [7:0] tx_byte;
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spi_slave spi (
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.clk(clk), .reset(reset),
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.sck(spi_sck), .mosi(spi_mosi), .ss_n(spi_ss_n), .miso(spi_miso),
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.selected(selected), .rx_valid(rx_valid), .rx_byte(rx_byte),
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.rx_is_first(rx_is_first), .tx_byte(tx_byte), .tx_loaded(tx_loaded)
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);
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reg is_read;
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reg [6:0] reg_addr;
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// DATA bytes are prefetched one ahead: prefetch_addr moves when a byte is loaded for
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// shifting, bytes_read only when it has been fully clocked out. Between transactions
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// prefetch_addr rewinds to bytes_read so the trailing prefetch is not lost.
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reg [CAPTURE_ADDR_WIDTH-1:0] bytes_read;
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wire reading_data = is_read && reg_addr == REG_DATA;
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function [7:0] gen_register(input [6:0] addr);
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reg [1:0] n;
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begin
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n = addr[3:2];
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if (addr[6:4] != 3'b011)
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gen_register = 8'h00;
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else case (addr[1:0])
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GEN_FLAGS: gen_register = {2'd0, healthy[n], sweep_done[n], gen_enable[n],
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too_many_dead[n], apt_failed[n], rct_failed[n]};
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GEN_RCT_EVENTS: gen_register = rct_events[n];
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GEN_APT_EVENTS: gen_register = apt_events[n];
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default: gen_register = sweep_done[n] ? dead_rings[n] : 8'h00;
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endcase
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end
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endfunction
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always @(*) begin
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case (reg_addr)
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REG_ID0: tx_byte = "S";
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REG_ID1: tx_byte = "T";
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REG_ID2: tx_byte = "R";
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REG_ID3: tx_byte = "X";
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REG_VERSION: tx_byte = VERSION;
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REG_FREQ_GATE: tx_byte = FREQ_GATE_BITS;
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REG_GENERATORS: tx_byte = GENERATORS;
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REG_RINGS: tx_byte = RINGS_PER_GEN;
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REG_SOURCE_A: tx_byte = {4'd0, source_a};
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REG_DECIM_HIGH: tx_byte = decimation[15:8];
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REG_DECIM_LOW: tx_byte = decimation[7:0];
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REG_STATUS: tx_byte = {4'd0, freq_valid, freq_busy, capture_done, capture_busy};
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REG_SOURCE_B: tx_byte = {4'd0, source_b};
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REG_MODE: tx_byte = {7'd0, pair_mode};
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REG_DATA: tx_byte = capture_byte;
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REG_RING_SELECT: tx_byte = ring_select;
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REG_FREQ_COUNT3: tx_byte = freq_count[31:24];
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REG_FREQ_COUNT2: tx_byte = freq_count[23:16];
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REG_FREQ_COUNT1: tx_byte = freq_count[15:8];
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REG_FREQ_COUNT0: tx_byte = freq_count[7:0];
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REG_GEN_ENABLE: tx_byte = {4'd0, gen_enable};
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REG_TEMPORAL: tx_byte = {4'd0, temporal};
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REG_FREQ_GEN: tx_byte = {6'd0, freq_gen};
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REG_HEALTHY: tx_byte = {4'd0, healthy};
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REG_RCT_CUTOFF: tx_byte = rct_cutoff;
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REG_APT_HIGH: tx_byte = {5'd0, apt_cutoff[10:8]};
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REG_APT_LOW: tx_byte = apt_cutoff[7:0];
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REG_MAX_DEAD: tx_byte = max_dead;
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REG_TRIAL_HIGH: tx_byte = trial_ms[15:8];
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REG_TRIAL_LOW: tx_byte = trial_ms[7:0];
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REG_STATS_CTRL: tx_byte = {7'd0, stats_von_neumann};
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REG_STATS: tx_byte = stats_byte;
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default: tx_byte = gen_register(reg_addr);
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endcase
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end
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always @(posedge clk) begin
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capture_start <= 1'b0;
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freq_start <= 1'b0;
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health_clear <= 1'b0;
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stats_restart <= 1'b0;
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if (reset) begin
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gen_enable <= {GENERATORS{1'b1}};
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temporal <= 4'd5;
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ring_select <= 8'd0;
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source_a <= 4'h0;
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source_b <= 4'h1;
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pair_mode <= 1'b0;
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decimation <= 16'd5;
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freq_gen <= 2'd0;
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rct_cutoff <= 8'd81; // 0.5 bits/bit claimed, alpha 2^-40
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apt_cutoff <= 11'd824; // same, 1024-bit window
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max_dead <= 8'd8; // measured sizing tolerates about 17
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health_clear <= 1'b1;
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trial_ms <= 16'd200;
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stats_von_neumann <= 1'b0;
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stats_index <= 8'd0;
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is_read <= 1'b0;
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reg_addr <= 7'd0;
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bytes_read <= {CAPTURE_ADDR_WIDTH{1'b0}};
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prefetch_addr <= {CAPTURE_ADDR_WIDTH{1'b0}};
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end else begin
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if (!selected)
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stats_index <= 8'd0;
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else if (tx_loaded && is_read && reg_addr == REG_STATS)
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stats_index <= stats_index + 8'd1;
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if (!selected)
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prefetch_addr <= bytes_read;
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else if (tx_loaded && reading_data)
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prefetch_addr <= prefetch_addr + 1'b1;
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if (rx_valid) begin
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if (rx_is_first) begin
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is_read <= rx_byte[7];
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reg_addr <= rx_byte[6:0];
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end else if (reading_data) begin
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bytes_read <= bytes_read + 1'b1;
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end else if (!is_read) begin
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case (reg_addr)
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REG_SOURCE_A: source_a <= rx_byte[3:0];
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REG_SOURCE_B: source_b <= rx_byte[3:0];
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REG_MODE: pair_mode <= rx_byte[0];
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REG_DECIM_HIGH: decimation[15:8] <= rx_byte;
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REG_DECIM_LOW: decimation[7:0] <= rx_byte;
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REG_RING_SELECT: if (rx_byte < RINGS_PER_GEN) ring_select <= rx_byte;
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REG_GEN_ENABLE: gen_enable <= rx_byte[GENERATORS-1:0];
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REG_TEMPORAL: if (rx_byte >= 8'd1 && rx_byte <= 8'd8) temporal <= rx_byte[3:0];
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REG_FREQ_GEN: freq_gen <= rx_byte[1:0];
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REG_HEALTH_CTRL: health_clear <= rx_byte[0];
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REG_RCT_CUTOFF: if (rx_byte >= 8'd2) rct_cutoff <= rx_byte;
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REG_APT_HIGH: apt_cutoff[10:8] <= rx_byte[2:0];
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REG_APT_LOW: apt_cutoff[7:0] <= rx_byte;
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REG_MAX_DEAD: max_dead <= rx_byte;
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REG_TRIAL_HIGH: trial_ms[15:8] <= rx_byte;
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REG_TRIAL_LOW: trial_ms[7:0] <= rx_byte;
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REG_STATS_CTRL: begin
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stats_von_neumann <= rx_byte[0];
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stats_restart <= rx_byte[1];
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end
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REG_CONTROL: begin
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if (rx_byte[0]) capture_start <= 1'b1;
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if (rx_byte[0] || rx_byte[1]) bytes_read <= {CAPTURE_ADDR_WIDTH{1'b0}};
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if (rx_byte[2]) freq_start <= 1'b1;
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end
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default: ;
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endcase
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end
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end
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end
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end
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endmodule
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