strix/fpga/sim
2026-10-25 17:48:20 +02:00
..
tb_amp_stage.v feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6) 2026-10-25 14:59:27 +02:00
tb_strix_core.v fix: hand GPIO0 to the WiFi module, count only healthy generators, shorten amplifier stage path (FPGA v9) 2026-10-25 17:48:20 +02:00