139 lines
4.3 KiB
Verilog
139 lines
4.3 KiB
Verilog
// Testbench for strix_core: SPI register access and a small raw capture read back in
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// two transactions. Rings are replaced by the SIM model in ring_osc.v.
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`timescale 1ns / 1ps
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module tb_strix_core;
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localparam CAPTURE_ADDR_WIDTH = 6; // 64-byte buffer keeps the simulation short
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localparam CAPTURE_BYTES = 1 << CAPTURE_ADDR_WIDTH;
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localparam SCK_HALF = 62.5; // 8 MHz SCK
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reg clk = 1'b0;
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always #4.1667 clk = ~clk; // 120 MHz
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reg reset = 1'b1;
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reg sck = 1'b0, mosi = 1'b0, ss_n = 1'b1;
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wire miso, done;
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strix_core #(.CAPTURE_ADDR_WIDTH(CAPTURE_ADDR_WIDTH)) dut (
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.clk(clk), .reset(reset),
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.spi_sck(sck), .spi_mosi(mosi), .spi_ss_n(ss_n), .spi_miso(miso),
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.capture_done(done)
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);
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integer errors = 0;
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task spi_byte(input [7:0] out, output [7:0] in);
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integer i;
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begin
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for (i = 7; i >= 0; i = i - 1) begin
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mosi = out[i];
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#SCK_HALF sck = 1'b1;
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in[i] = miso;
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#SCK_HALF sck = 1'b0;
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end
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end
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endtask
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task write_reg(input [6:0] addr, input [7:0] value);
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reg [7:0] dummy;
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begin
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ss_n = 1'b0; #SCK_HALF;
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spi_byte({1'b0, addr}, dummy);
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spi_byte(value, dummy);
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#SCK_HALF ss_n = 1'b1; #(4 * SCK_HALF);
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end
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endtask
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task read_reg(input [6:0] addr, output [7:0] value);
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reg [7:0] dummy;
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begin
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ss_n = 1'b0; #SCK_HALF;
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spi_byte({1'b1, addr}, dummy);
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spi_byte(8'h00, value);
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#SCK_HALF ss_n = 1'b1; #(4 * SCK_HALF);
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end
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endtask
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task read_data(input integer first, input integer count);
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reg [7:0] dummy, value;
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integer i;
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begin
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ss_n = 1'b0; #SCK_HALF;
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spi_byte({1'b1, 7'h10}, dummy);
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for (i = 0; i < count; i = i + 1) begin
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spi_byte(8'h00, value);
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if (value !== dut.capture.buffer[first + i]) begin
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$display("FAIL data[%0d]: got %02x, expected %02x", first + i, value, dut.capture.buffer[first + i]);
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errors = errors + 1;
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end
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end
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#SCK_HALF ss_n = 1'b1; #(4 * SCK_HALF);
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end
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endtask
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task expect(input [7:0] got, input [7:0] want, input [8*16-1:0] what);
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if (got !== want) begin
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$display("FAIL %0s: got %02x, expected %02x", what, got, want);
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errors = errors + 1;
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end
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endtask
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reg [7:0] v;
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integer n;
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initial begin
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#100 reset = 1'b0;
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#200;
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read_reg(7'h00, v); expect(v, "S", "ID0");
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read_reg(7'h03, v); expect(v, "X", "ID3");
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read_reg(7'h04, v); expect(v, 8'h01, "VERSION");
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write_reg(7'h08, 8'h01);
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write_reg(7'h09, 8'h00);
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write_reg(7'h0A, 8'h03);
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read_reg(7'h08, v); expect(v, 8'h01, "SRC");
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read_reg(7'h0A, v); expect(v, 8'h03, "DECIM_L");
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write_reg(7'h0B, 8'h01);
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n = 0;
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read_reg(7'h0C, v);
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while (v[1] !== 1'b1 && n < 1000) begin
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read_reg(7'h0C, v);
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n = n + 1;
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end
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expect(v, 8'h02, "STATUS");
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if (done !== 1'b1) begin
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$display("FAIL capture_done not set");
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errors = errors + 1;
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end
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// Captured bytes must be defined and vary, otherwise the comparisons below prove nothing.
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n = 0;
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for (v = 0; v < CAPTURE_BYTES - 1; v = v + 1) begin
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if (^dut.capture.buffer[v] === 1'bx) begin
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$display("FAIL mem[%0d] undefined", v);
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errors = errors + 1;
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end
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if (dut.capture.buffer[v] !== dut.capture.buffer[v + 1]) n = n + 1;
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end
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if (n == 0) begin
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$display("FAIL capture buffer is constant");
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errors = errors + 1;
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end
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// Read the buffer in two transactions; the second must continue where the first stopped.
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read_data(0, CAPTURE_BYTES / 2);
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read_data(CAPTURE_BYTES / 2, CAPTURE_BYTES / 2);
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// Rewind and read the first bytes again.
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write_reg(7'h0B, 8'h02);
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read_data(0, 4);
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if (errors == 0) $display("PASS");
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else $display("%0d error(s)", errors);
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$finish;
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end
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endmodule
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