69 lines
2.4 KiB
Verilog
69 lines
2.4 KiB
Verilog
// SPI mode 0 slave, oversampled in the system clock domain (SCK must stay below about a
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// tenth of clk). MISO changes a few clk cycles after each SCK falling edge, which leaves
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// enough margin for the master's next rising edge at 8 MHz SCK with a 120 MHz clk.
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module spi_slave (
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input wire clk,
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input wire reset,
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input wire sck,
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input wire mosi,
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input wire ss_n,
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output wire miso,
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output wire selected, // ss_n asserted (synchronized)
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output reg rx_valid, // pulse: rx_byte holds a complete byte
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output reg [7:0] rx_byte,
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output reg rx_is_first, // rx_byte is the first byte of the transaction
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input wire [7:0] tx_byte, // sampled when the next byte starts shifting out
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output reg tx_loaded // pulse: tx_byte was taken
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);
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reg [2:0] sck_history, ss_n_history;
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reg [1:0] mosi_history;
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always @(posedge clk) begin
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sck_history <= {sck_history[1:0], sck};
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ss_n_history <= {ss_n_history[1:0], ss_n};
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mosi_history <= {mosi_history[0], mosi};
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end
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wire sck_rising = (sck_history[2:1] == 2'b01);
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wire sck_falling = (sck_history[2:1] == 2'b10);
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wire mosi_bit = mosi_history[1];
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assign selected = ~ss_n_history[1];
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reg [2:0] bit_count;
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reg [6:0] rx_shift;
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reg [7:0] tx_shift;
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reg expecting_first;
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assign miso = tx_shift[7];
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always @(posedge clk) begin
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rx_valid <= 1'b0;
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tx_loaded <= 1'b0;
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if (reset || !selected) begin
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bit_count <= 3'd0;
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expecting_first <= 1'b1;
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tx_shift <= 8'h00; // MISO is don't-care during the command byte
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end else begin
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if (sck_rising) begin
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rx_shift <= {rx_shift[5:0], mosi_bit};
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bit_count <= bit_count + 3'd1;
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if (bit_count == 3'd7) begin
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rx_valid <= 1'b1;
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rx_byte <= {rx_shift, mosi_bit};
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rx_is_first <= expecting_first;
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expecting_first <= 1'b0;
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end
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end
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if (sck_falling) begin
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if (bit_count == 3'd0) begin
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tx_shift <= tx_byte;
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tx_loaded <= 1'b1;
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end else begin
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tx_shift <= {tx_shift[6:0], 1'b0};
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end
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end
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end
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end
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endmodule
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