131 lines
5.5 KiB
Verilog
131 lines
5.5 KiB
Verilog
// Per-second trials in the format of Global Consciousness Project (GCP) style network analyses,
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// running alongside the other outputs. Every TRIAL_MS milliseconds (one second) each generator
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// yields:
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// - the sum of the first SAMPLE_BITS bits of the second, the GCP trial (expected 100, sd 7.07);
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// - the sum of all its bits during the second, for a full-rate z-score.
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// Both use XOR-masked bits: bit i of the second is inverted when i is odd, so a constant bias
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// cancels. All generators deliver in lockstep, so one bit count serves them all; generators that
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// were not healthy for the whole second are flagged in the snapshot, not excluded from counting.
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//
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// Snapshot layout (big-endian), latched at the end of each second:
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// 0-3 sequence number, starting at 1 (0: no second completed yet)
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// 4 generators healthy during the whole second (bit g)
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// 5 SAMPLE_BITS
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// 6-7 0
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// 8-11 bits per generator during the second
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// 12+5g generator g: sample sum (1), masked ones during the second (4)
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// 32-35 sequence number again; a mismatch with bytes 0-3 means a torn read
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module gcp_block #(
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parameter GENERATORS = 4,
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parameter SAMPLE_BITS = 200,
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parameter TRIAL_MS = 1000,
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parameter TICK_CYCLES = 120000 // clk cycles per millisecond
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) (
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input wire clk,
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input wire reset,
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input wire [GENERATORS-1:0] gen_bit,
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input wire gen_valid,
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input wire [GENERATORS-1:0] healthy,
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input wire [7:0] read_index,
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output reg [7:0] read_byte, // one cycle after read_index
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output reg trial_end // pulse: a new snapshot is available
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);
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localparam SNAPSHOT_BYTES = 12 + 5 * GENERATORS + 4;
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localparam [7:0] SAMPLE_SIZE = SAMPLE_BITS;
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// Trial timing
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reg [16:0] tick_count;
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reg [15:0] ms_count;
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wire tick = (tick_count == TICK_CYCLES - 1);
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always @(posedge clk) begin
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trial_end <= 1'b0;
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if (reset) begin
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tick_count <= 17'd0;
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ms_count <= 16'd0;
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end else begin
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tick_count <= tick ? 17'd0 : tick_count + 17'd1;
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if (tick && ms_count == TRIAL_MS - 1) begin
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ms_count <= 16'd0;
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trial_end <= 1'b1;
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end else if (tick) begin
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ms_count <= ms_count + 16'd1;
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end
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end
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end
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// Counters. As in stats_block, the bit arriving in the trial_end cycle opens the next second.
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reg [31:0] bit_count;
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reg [7:0] sampled; // bits taken into the sample sums this second
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reg odd; // the next bit has an odd index in the second
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reg [7:0] sample_sum [0:GENERATORS-1];
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reg [31:0] masked_ones [0:GENERATORS-1];
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reg [31:0] sequence_number;
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reg [GENERATORS-1:0] healthy_during;
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wire mask = trial_end ? 1'b0 : odd;
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wire in_sample = trial_end || sampled < SAMPLE_BITS;
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wire [GENERATORS-1:0] masked = gen_bit ^ {GENERATORS{mask}};
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reg [8*SNAPSHOT_BYTES-1:0] snapshot_next;
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reg [7:0] snapshot [0:SNAPSHOT_BYTES-1];
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integer k;
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always @(*) begin
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snapshot_next = {SNAPSHOT_BYTES{8'h00}};
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snapshot_next[8*SNAPSHOT_BYTES-1 -: 96] = {sequence_number,
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{8-GENERATORS{1'b0}}, healthy_during & healthy,
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SAMPLE_SIZE, 16'd0, bit_count};
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for (k = 0; k < GENERATORS; k = k + 1)
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snapshot_next[8*SNAPSHOT_BYTES-1-96-40*k -: 40] = {sample_sum[k], masked_ones[k]};
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snapshot_next[31:0] = sequence_number;
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end
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integer g, b;
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always @(posedge clk) begin
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if (reset) begin
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bit_count <= 32'd0;
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sampled <= 8'd0;
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odd <= 1'b0;
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sequence_number <= 32'd1;
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healthy_during <= {GENERATORS{1'b1}};
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for (g = 0; g < GENERATORS; g = g + 1) begin
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sample_sum[g] <= 8'd0;
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masked_ones[g] <= 32'd0;
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end
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end else begin
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if (gen_valid) begin
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bit_count <= (trial_end ? 32'd0 : bit_count) + 32'd1;
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sampled <= in_sample ? (trial_end ? 8'd0 : sampled) + 8'd1 : sampled;
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odd <= ~mask;
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for (g = 0; g < GENERATORS; g = g + 1) begin
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sample_sum[g] <= (trial_end ? 8'd0 : sample_sum[g]) + (in_sample && masked[g]);
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masked_ones[g] <= (trial_end ? 32'd0 : masked_ones[g]) + masked[g];
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end
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end else if (trial_end) begin
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bit_count <= 32'd0;
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sampled <= 8'd0;
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odd <= 1'b0;
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for (g = 0; g < GENERATORS; g = g + 1) begin
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sample_sum[g] <= 8'd0;
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masked_ones[g] <= 32'd0;
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end
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end
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if (trial_end) begin
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for (b = 0; b < SNAPSHOT_BYTES; b = b + 1)
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snapshot[b] <= snapshot_next[8*(SNAPSHOT_BYTES-1-b) +: 8];
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sequence_number <= sequence_number + 32'd1;
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healthy_during <= healthy;
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end else begin
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healthy_during <= healthy_during & healthy;
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end
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end
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end
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always @(posedge clk)
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read_byte <= (read_index < SNAPSHOT_BYTES) ? snapshot[read_index] : 8'h00;
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endmodule
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