// STRIX top level for the Arduino MKR Vidor 4000. Port names match the Vidor constraints
// in strix.qsf; unused board pins are left out and stay tri-stated.
module strix (
    input  wire        iCLK,       // 48 MHz from the SAMD21 (GCLK0)

    inout  wire [14:0] bMKR_D,     // header D0-D14, shared with the SAMD21
    inout  wire [6:0]  bMKR_A,     // header A0-A6, shared with the SAMD21

    // NINA-W102 WiFi module
    inout  wire        bWM_PIO1,   // NINA MISO
    inout  wire        bWM_PIO7,   // NINA ACK (GPIO33)
    inout  wire        bWM_PIO27,  // NINA GPIO0
    inout  wire        bWM_PIO28,  // NINA SS (GPIO5)
    inout  wire        bWM_PIO29,  // NINA SCK
    inout  wire        bWM_PIO36,  // NINA MOSI
    input  wire        iWM_TX,
    inout  wire        oWM_RX,
    inout  wire        oWM_RESET,

    output wire        oSAM_INT    // interrupt line to the SAMD21
);

    // Clock and reset

    wire clk, pll_locked;

    sys_pll pll (.inclk0(iCLK), .c0(clk), .locked(pll_locked));

    reg [2:0] reset_pipe = 3'b111;
    always @(posedge clk or negedge pll_locked)
        if (!pll_locked) reset_pipe <= 3'b111;
        else             reset_pipe <= {reset_pipe[1:0], 1'b0};
    wire reset = reset_pipe[2];

    // NINA pass-through: the SAMD21 talks to the WiFi module as if wired directly.

    wire sam_nina_mosi   = bMKR_D[8];   // SERCOM1
    wire sam_nina_sck    = bMKR_D[9];
    wire sam_nina_ss     = bMKR_D[5];
    wire sam_nina_gpio0  = bMKR_D[6];
    wire sam_nina_resetn = bMKR_D[7];
    wire sam_uart_tx     = bMKR_D[14];

    assign bWM_PIO36 = sam_nina_mosi;
    assign bWM_PIO29 = sam_nina_sck;
    assign bWM_PIO28 = sam_nina_ss;
    assign bWM_PIO27 = sam_nina_gpio0;
    assign oWM_RESET = sam_nina_resetn;
    assign oWM_RX    = sam_uart_tx;
    assign bWM_PIO1  = 1'bz;            // inputs from NINA
    assign bWM_PIO7  = 1'bz;

    wire nina_miso    = bWM_PIO1;       // to D10
    wire nina_ack     = bWM_PIO7;       // to D4
    wire nina_uart_tx = iWM_TX;         // to D13

    // STRIX SPI link on SAMD21 SERCOM0 alternate pins: A3 MOSI, A4 SCK, A5 SS, A6 MISO.

    wire strix_mosi = bMKR_A[3];
    wire strix_sck  = bMKR_A[4];
    wire strix_ss_n = bMKR_A[5];
    wire strix_miso, capture_done;

    strix_core core (
        .clk(clk), .reset(reset),
        .spi_sck(strix_sck), .spi_mosi(strix_mosi), .spi_ss_n(strix_ss_n),
        .spi_miso(strix_miso), .capture_done(capture_done)
    );

    assign oSAM_INT = capture_done;

    // Header pins driven by the FPGA; all others are inputs.

    genvar d;
    generate
        for (d = 0; d < 15; d = d + 1) begin : header_d
            assign bMKR_D[d] = (d == 4)  ? nina_ack :
                               (d == 10) ? nina_miso :
                               (d == 13) ? nina_uart_tx : 1'bz;
        end
    endgenerate

    assign bMKR_A = {strix_miso, 6'bzzzzzz};

endmodule