Commit graph

3 commits

Author SHA1 Message Date
randogoth
0332d8eb33 feat: add FPGA raw jitter capture design with SPI register interface 2026-10-25 12:25:25 +02:00
randogoth
3ee8a5c3db chore: add Quartus Prime Lite toolchain via nix flake in devbox 2026-10-25 12:09:56 +02:00
randogoth
816ae0fc75 init 2024-07-21 18:19:27 +03:00