randogoth/strix
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2 commits

Author SHA1 Message Date
randogoth
504b00752a feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2) 2026-10-25 13:03:53 +02:00
randogoth
d51a6c0ca8 feat: add capture sketch, Vidor image tool and jitter analysis script 2026-10-25 12:30:16 +02:00