randogoth/strix
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions
15 commits 1 branch 0 tags 416 KiB
Commit graph

2 commits

Author SHA1 Message Date
randogoth
504b00752a feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2) 2026-10-25 13:03:53 +02:00
randogoth
0332d8eb33 feat: add FPGA raw jitter capture design with SPI register interface 2026-10-25 12:25:25 +02:00