feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)
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randogoth
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11 changed files with 741 additions and 58 deletions
97
fpga/sim/tb_amp_stage.v
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97
fpga/sim/tb_amp_stage.v
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@ -0,0 +1,97 @@
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// Testbench for amp_stage: random input bits against a reference model of both modes, plus a
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// statistical check that a biased input comes out more biased.
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`timescale 1ns / 1ps
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module tb_amp_stage;
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reg clk = 1'b0;
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always #5 clk = ~clk;
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reg restart = 1'b1, mode = 1'b0, in_valid = 1'b0, in_bit = 1'b0;
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reg [15:0] param = 16'd1;
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wire out_valid, out_bit;
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amp_stage dut (
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.clk(clk), .restart(restart), .mode(mode), .param(param),
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.in_valid(in_valid), .in_bit(in_bit), .out_valid(out_valid), .out_bit(out_bit)
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);
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integer errors = 0;
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// Reference model, advanced on the same edges as the stage
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integer model_position, model_seen, model_ones, model_bound, dut_outputs, ones_out;
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reg model_valid, model_bit;
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always @(posedge clk) begin
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model_valid = 1'b0;
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if (restart) begin
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model_position = 0; model_seen = 0; model_ones = 0;
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end else if (in_valid) begin
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if (mode == 1'b0) begin
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model_bound = param; // signed copy: -param would wrap as unsigned
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model_position = model_position + (in_bit ? 1 : -1);
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if (model_position >= model_bound || model_position <= -model_bound) begin
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model_valid = 1'b1; model_bit = model_position > 0; model_position = 0;
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end
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end else begin
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model_seen = model_seen + 1; model_ones = model_ones + in_bit;
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if (model_seen >= param) begin
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model_valid = 1'b1; model_bit = 2 * model_ones > model_seen;
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model_seen = 0; model_ones = 0;
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end
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end
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end
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end
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// The model and the stage both update on the rising edge; compare in between.
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always @(negedge clk) if (!restart) begin
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if (out_valid !== model_valid || (out_valid && out_bit !== model_bit)) begin
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if (errors < 5) $display("FAIL at %0t: out %b/%b, model %b/%b", $time, out_valid, out_bit,
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model_valid, model_bit);
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errors = errors + 1;
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end
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if (out_valid) begin
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dut_outputs = dut_outputs + 1;
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ones_out = ones_out + out_bit;
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end
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end
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task run(input m, input [15:0] p, input integer cycles, input integer probability_permille);
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integer i;
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begin
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@(negedge clk);
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mode = m; param = p; restart = 1'b1;
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@(negedge clk);
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restart = 1'b0; dut_outputs = 0; ones_out = 0;
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for (i = 0; i < cycles; i = i + 1) begin
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in_valid = ({$random} % 3) != 0;
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in_bit = ({$random} % 1000) < probability_permille;
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@(negedge clk);
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end
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in_valid = 1'b0;
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@(negedge clk);
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end
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endtask
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initial begin
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run(1'b0, 16'd1, 2000, 500);
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run(1'b0, 16'd5, 20000, 500);
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run(1'b0, 16'd16, 50000, 500);
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run(1'b1, 16'd1, 2000, 500);
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run(1'b1, 16'd7, 20000, 500);
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run(1'b1, 16'd8, 20000, 500); // even window: ties output 0
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// Amplification: 55% ones in, random walk bound 10 -> about 88% ones out
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// (P = 1 / (1 + ((1-p)/p)^n) = 1 / (1 + (0.45/0.55)^10) = 0.88)
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run(1'b0, 16'd10, 400000, 550);
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if (dut_outputs < 500 || ones_out * 100 < dut_outputs * 83 || ones_out * 100 > dut_outputs * 93) begin
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$display("FAIL amplification: %0d of %0d outputs are 1", ones_out, dut_outputs);
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errors = errors + 1;
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end
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if (errors == 0) $display("PASS (amplified %0d/%0d ones)", ones_out, dut_outputs);
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else $display("%0d error(s)", errors);
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$finish;
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end
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endmodule
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@ -1,7 +1,7 @@
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// Testbench for strix_core: register access, generator XOR logic checked against the sampled
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// ring outputs, captures read back across transactions, generator enable, the frequency
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// counter, the health monitors with injected faults, and the statistics snapshots against a
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// reference model. Rings are replaced by the SIM model in ring_osc.v.
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// counter, the health monitors with injected faults, the statistics snapshots against a
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// reference model, and the bias amplifier's bit counts in several configurations. Rings are replaced by the SIM model in ring_osc.v.
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`timescale 1ns / 1ps
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module tb_strix_core;
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@ -17,10 +17,16 @@ module tb_strix_core;
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REG_DATA = 7'h10, REG_RING_SELECT = 7'h11, REG_FREQ_COUNT0 = 7'h15,
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REG_GEN_ENABLE = 7'h16, REG_TEMPORAL = 7'h17, REG_FREQ_GEN = 7'h18,
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REG_HEALTHY = 7'h20, REG_HEALTH_CTRL = 7'h21, REG_TRIAL_LOW = 7'h27,
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REG_STATS_CTRL = 7'h28, REG_STATS = 7'h40;
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REG_STATS_CTRL = 7'h28, REG_STATS = 7'h40, REG_AMP = 7'h42,
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REG_AMP_CTRL = 7'h50, REG_AMP_SOURCES = 7'h51, REG_AMP_SUB_MS = 7'h52,
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REG_AMP_SUBS = 7'h53, REG_AMP_STAGE = 7'h54;
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localparam AMP_SNAPSHOT_BYTES = 44;
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localparam SNAPSHOT_BYTES = 72;
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localparam TICK_CYCLES = 1500; // 1 "ms" = 12.5 us: a 10 "ms" trial outlasts a 72-byte read
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localparam TRIAL_BITS = 10 * TICK_CYCLES / 5; // 10 "ms" trials at temporal 5
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// Amplifier trials in the tests: 3 sub-trials of 2 "ms" -> 9000 clk cycles -> 1800 output
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// bits per generator at temporal 5
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localparam AMP_GEN_BITS = 3 * 2 * TICK_CYCLES / 5;
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// Per-generator health registers
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function [6:0] gen_reg(input integer generator, input integer index);
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@ -219,6 +225,43 @@ module tb_strix_core;
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end
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endtask
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reg [7:0] amp [0:AMP_SNAPSHOT_BYTES-1];
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function [31:0] amp_word(input integer index);
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amp_word = {amp[index], amp[index+1], amp[index+2], amp[index+3]};
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endfunction
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// Configures the amplifier (stage bounds or windows, random walk), restarts it, waits for its
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// second trial and reads that trial's snapshot.
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task amp_trial(input [3:0] sources, input von_neumann, input [15:0] p0, input [15:0] p1, input [15:0] p2);
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reg [7:0] dummy;
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integer i;
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begin
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write_reg(REG_AMP_SOURCES, sources);
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write_reg(REG_AMP_STAGE + 1, p0 >> 8); write_reg(REG_AMP_STAGE + 2, p0);
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write_reg(REG_AMP_STAGE + 4, p1 >> 8); write_reg(REG_AMP_STAGE + 5, p1);
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write_reg(REG_AMP_STAGE + 7, p2 >> 8); write_reg(REG_AMP_STAGE + 8, p2);
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write_reg(REG_AMP_CTRL, {6'd0, 1'b1, von_neumann}); // restart
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@(posedge dut.amp_trial_end); @(posedge dut.amp_trial_end); #200;
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ss_n = 1'b0; #SCK_HALF;
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spi_byte({1'b1, REG_AMP}, dummy);
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for (i = 0; i < AMP_SNAPSHOT_BYTES; i = i + 1) spi_byte(8'h00, amp[i]);
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#SCK_HALF ss_n = 1'b1; #(4 * SCK_HALF);
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if (amp_word(0) !== amp_word(AMP_SNAPSHOT_BYTES - 4) || amp_word(0) !== 32'd1) begin
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$display("FAIL amplifier snapshot sequence %0d/%0d", amp_word(0), amp_word(AMP_SNAPSHOT_BYTES - 4));
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errors = errors + 1;
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end
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if (amp[4][5]) begin $display("FAIL amplifier merge overflow"); errors = errors + 1; end
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end
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endtask
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task expect_range(input integer got, input integer low, input integer high, input [8*24-1:0] what);
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if (got < low || got > high) begin
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$display("FAIL %0s: %0d not in %0d..%0d", what, got, low, high);
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errors = errors + 1;
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end
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endtask
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task wait_trial_end;
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begin
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@(posedge dut.trial_end);
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@ -237,7 +280,7 @@ module tb_strix_core;
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// Identification
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read_reg(REG_ID0, v); expect(v, "S", "ID0");
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read_reg(REG_ID3, v); expect(v, "X", "ID3");
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read_reg(REG_VERSION, v); expect(v, 8'h05, "VERSION");
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read_reg(REG_VERSION, v); expect(v, 8'h06, "VERSION");
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read_reg(REG_GENERATORS, v); expect(v, 8'd4, "GENERATORS");
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read_reg(REG_RINGS, v); expect(v, RINGS, "RINGS");
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read_reg(REG_TEMPORAL, v); expect(v, 8'd5, "TEMPORAL");
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@ -358,6 +401,34 @@ module tb_strix_core;
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end
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write_reg(REG_STATS_CTRL, 8'h00);
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// Bias amplifier
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write_reg(REG_AMP_SUB_MS, 8'd2);
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write_reg(REG_AMP_SUBS, 8'd3);
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// Passthrough (all bounds 1): every generator bit appears once on the bias path
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amp_trial(4'hF, 1'b0, 16'd1, 16'd1, 16'd1);
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expect(amp[4] & 8'h0F, 8'h0F, "amp sources");
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expect(amp[5], 8'd3, "amp sub-trials");
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expect_range(amp_word(8), 4 * AMP_GEN_BITS - 8, 4 * AMP_GEN_BITS + 8, "amp passthrough bits");
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expect_range(amp_word(24), 4 * AMP_GEN_BITS - 8, 4 * AMP_GEN_BITS + 8, "amp autocorr bits");
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expect_range(amp_word(12), 4 * AMP_GEN_BITS / 3, 4 * AMP_GEN_BITS * 2 / 3, "amp passthrough ones");
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if (amp[20] == 0) begin $display("FAIL amplifier cast no votes"); errors = errors + 1; end
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// One source only
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amp_trial(4'h1, 1'b0, 16'd1, 16'd1, 16'd1);
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expect(amp[4] & 8'h0F, 8'h01, "amp single source");
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expect_range(amp_word(8), AMP_GEN_BITS - 2, AMP_GEN_BITS + 2, "amp single-source bits");
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// Random walk bound 2 in stage 1: about a quarter of the bits (4 steps per output)
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amp_trial(4'hF, 1'b0, 16'd2, 16'd1, 16'd1);
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expect_range(amp_word(8), 4 * AMP_GEN_BITS / 6, 4 * AMP_GEN_BITS / 3, "amp bound-2 bits");
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// Von Neumann keeps about a quarter of the bits
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amp_trial(4'hF, 1'b1, 16'd1, 16'd1, 16'd1);
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expect(amp[4] & 8'h10, 8'h10, "amp von Neumann flag");
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expect_range(amp_word(8), 4 * AMP_GEN_BITS / 6, 4 * AMP_GEN_BITS / 3, "amp von Neumann bits");
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write_reg(REG_AMP_CTRL, 8'h00);
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if (xor_checks < 100) begin
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$display("FAIL only %0d temporal XOR checks ran", xor_checks);
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errors = errors + 1;
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