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feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)

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randogoth 2026-10-25 14:59:27 +02:00
parent 5305d66102
commit 8541cce59c
11 changed files with 741 additions and 58 deletions
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14
fpga/rtl/stats_block.v
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@ -86,9 +86,10 @@ module stats_block #(
reg [3:0] healthy_during;
reg von_neumann_during;
// The snapshot is latched as one flat byte string (byte 0 in the top bits), so reading it
// is a plain byte multiplexer.
reg [8*SNAPSHOT_BYTES-1:0] snapshot, snapshot_next;
// The snapshot is assembled as one flat byte string (byte 0 in the top bits) and latched
// into a byte array, so reading it is a plain byte multiplexer on the index.
reg [8*SNAPSHOT_BYTES-1:0] snapshot_next;
reg [7:0] snapshot [0:SNAPSHOT_BYTES-1]; // byte 0 first, indexed directly
integer k;
always @(*) begin
@ -100,7 +101,7 @@ module stats_block #(
snapshot_next[31:0] = sequence_number;
end
integer c;
integer c, b;
always @(posedge clk) begin
if (reset || restart) begin
sequence_number <= 32'd0;
@ -129,7 +130,8 @@ module stats_block #(
end
end
if (trial_end) begin
snapshot <= snapshot_next;
for (b = 0; b < SNAPSHOT_BYTES; b = b + 1)
snapshot[b] <= snapshot_next[8*(SNAPSHOT_BYTES-1-b) +: 8];
sequence_number <= sequence_number + 32'd1;
healthy_during <= healthy;
von_neumann_during <= von_neumann;
@ -143,6 +145,6 @@ module stats_block #(
// Snapshot read-out, registered: the byte for read_index appears one cycle later.
always @(posedge clk)
read_byte <= (read_index < SNAPSHOT_BYTES) ? snapshot[8*(SNAPSHOT_BYTES-1-read_index) +: 8] : 8'h00;
read_byte <= (read_index < SNAPSHOT_BYTES) ? snapshot[read_index] : 8'h00;
endmodule