feat: add two-path bias amplifier with random walk and majority vote stages (FPGA v6)
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randogoth
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11 changed files with 741 additions and 58 deletions
186
fpga/rtl/bias_amplifier.v
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186
fpga/rtl/bias_amplifier.v
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// Bias amplifier with two paths fed by the selected healthy generators:
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// path 0 (bias): the generator bits themselves;
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// path 1 (autocorrelation): each bit XNOR the previous bit of the same generator, so
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// positive lag-1 autocorrelation becomes an excess of ones.
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// An optional von Neumann extractor per generator runs before both paths.
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//
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// Trials consist of `subtrials` sub-trials of `sub_ms` milliseconds. Each sub-trial votes with
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// the majority of its amplified bits (no vote on a tie or without bits); the trial result is
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// the majority of the votes.
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//
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// Snapshot layout (big-endian), latched at each trial end:
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// 0-3 trial sequence number
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// 4 bits 3:0 generators used during the whole trial, bit 4 von Neumann during the
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// whole trial, bit 5 merge overflow since restart (should never be set)
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// 5 sub-trials per trial
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// 6 sub-trial length in ms
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// 7 0
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// 8+16p path p: amplified bits (4), ones (4), votes (2), voted (2), vote count (1),
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// result (1: bit 0 trial bit, bit 1 trial valid), 0 (2)
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// 40-43 trial sequence number again; a mismatch with bytes 0-3 means a torn read
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module bias_amplifier #(
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parameter GENERATORS = 4,
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parameter TICK_CYCLES = 120000 // clk cycles per millisecond
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) (
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input wire clk,
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input wire reset,
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input wire [GENERATORS-1:0] gen_bit,
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input wire gen_valid, // all generators deliver in lockstep
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input wire [GENERATORS-1:0] sources, // selected and healthy generators
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input wire von_neumann,
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input wire [2:0] stage_mode,
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input wire [47:0] stage_param,
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input wire [7:0] sub_ms,
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input wire [3:0] subtrials,
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input wire restart,
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input wire [7:0] read_index,
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output reg [7:0] read_byte, // one cycle after read_index
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output reg trial_end
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);
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localparam SNAPSHOT_BYTES = 44;
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wire start_over = reset || restart;
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// Von Neumann (01 -> 0, 10 -> 1) and autocorrelation conversion per generator
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reg [GENERATORS-1:0] pair_first, have_first, previous_bit, has_previous;
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wire [GENERATORS-1:0] vn_valid = von_neumann ? (gen_valid ? have_first & (gen_bit ^ pair_first) : {GENERATORS{1'b0}})
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: {GENERATORS{gen_valid}};
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wire [GENERATORS-1:0] vn_bit = von_neumann ? pair_first : gen_bit;
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wire [GENERATORS-1:0] bias_valid = vn_valid & sources;
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wire [GENERATORS-1:0] ac_valid = vn_valid & has_previous & sources;
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wire [GENERATORS-1:0] ac_bit = ~(vn_bit ^ previous_bit);
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always @(posedge clk) begin
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if (start_over || !von_neumann) begin
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have_first <= {GENERATORS{1'b0}};
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end else if (gen_valid) begin
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have_first <= ~have_first;
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pair_first <= gen_bit;
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end
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if (start_over) begin
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has_previous <= {GENERATORS{1'b0}};
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end else begin
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has_previous <= has_previous | vn_valid;
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previous_bit <= (vn_valid & vn_bit) | (~vn_valid & previous_bit);
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end
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end
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// Sub-trial and trial timing
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reg [16:0] tick_count;
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reg [7:0] ms_count;
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reg [3:0] sub_index;
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reg sub_end;
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wire tick = (tick_count == TICK_CYCLES - 1);
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always @(posedge clk) begin
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sub_end <= 1'b0;
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trial_end <= 1'b0;
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if (start_over) begin
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tick_count <= 17'd0;
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ms_count <= 8'd0;
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sub_index <= 4'd0;
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end else begin
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tick_count <= tick ? 17'd0 : tick_count + 17'd1;
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if (tick) begin
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if (ms_count + 8'd1 >= sub_ms) begin
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ms_count <= 8'd0;
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sub_end <= 1'b1;
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end else begin
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ms_count <= ms_count + 8'd1;
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end
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end
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// trial_end follows the last sub_end by one cycle, once its vote is registered.
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if (sub_end) begin
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if (sub_index + 4'd1 >= subtrials) begin
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sub_index <= 4'd0;
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trial_end <= 1'b1;
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end else begin
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sub_index <= sub_index + 4'd1;
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end
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end
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end
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end
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// Paths
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wire [31:0] trial_bits [0:1];
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wire [31:0] trial_ones [0:1];
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wire [15:0] votes [0:1];
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wire [15:0] voted [0:1];
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wire [1:0] overflow;
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amp_path #(.GENERATORS(GENERATORS)) bias_path (
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.clk(clk), .restart(start_over), .in_valid(bias_valid), .in_bit(vn_bit),
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.stage_mode(stage_mode), .stage_param(stage_param),
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.sub_end(sub_end), .sub_index(sub_index), .trial_end(trial_end),
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.trial_bits(trial_bits[0]), .trial_ones(trial_ones[0]),
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.votes(votes[0]), .voted(voted[0]), .overflow(overflow[0])
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);
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amp_path #(.GENERATORS(GENERATORS)) autocorrelation_path (
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.clk(clk), .restart(start_over), .in_valid(ac_valid), .in_bit(ac_bit),
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.stage_mode(stage_mode), .stage_param(stage_param),
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.sub_end(sub_end), .sub_index(sub_index), .trial_end(trial_end),
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.trial_bits(trial_bits[1]), .trial_ones(trial_ones[1]),
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.votes(votes[1]), .voted(voted[1]), .overflow(overflow[1])
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);
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// Snapshot
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function [4:0] count_ones(input [15:0] value);
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integer b;
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begin
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count_ones = 5'd0;
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for (b = 0; b < 16; b = b + 1) count_ones = count_ones + value[b];
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end
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endfunction
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function [127:0] path_bytes(input [31:0] bits, input [31:0] ones, input [15:0] vote, input [15:0] cast);
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reg [4:0] cast_count, one_votes;
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reg valid, result;
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begin
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cast_count = count_ones(cast);
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one_votes = count_ones(vote & cast);
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valid = cast_count != 0 && {one_votes, 1'b0} != {1'b0, cast_count};
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result = {one_votes, 1'b0} > {1'b0, cast_count};
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path_bytes = {bits, ones, vote, cast, 3'd0, cast_count, 6'd0, valid, result, 16'd0};
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end
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endfunction
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reg [31:0] sequence_number;
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reg [GENERATORS-1:0] sources_during;
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reg von_neumann_during;
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reg [7:0] snapshot [0:SNAPSHOT_BYTES-1]; // byte 0 first, indexed directly
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wire [8*SNAPSHOT_BYTES-1:0] snapshot_next = {
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sequence_number,
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2'd0, |overflow, von_neumann_during & von_neumann, sources_during & sources,
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4'd0, subtrials, sub_ms, 8'd0,
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path_bytes(trial_bits[0], trial_ones[0], votes[0], voted[0]),
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path_bytes(trial_bits[1], trial_ones[1], votes[1], voted[1]),
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sequence_number
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};
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integer k;
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always @(posedge clk) begin
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if (start_over) begin
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sequence_number <= 32'd0;
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sources_during <= sources;
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von_neumann_during <= von_neumann;
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end else if (trial_end) begin
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for (k = 0; k < SNAPSHOT_BYTES; k = k + 1)
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snapshot[k] <= snapshot_next[8*(SNAPSHOT_BYTES-1-k) +: 8];
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sequence_number <= sequence_number + 32'd1;
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sources_during <= sources;
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von_neumann_during <= von_neumann;
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end else begin
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sources_during <= sources_during & sources;
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von_neumann_during <= von_neumann_during & von_neumann;
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end
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read_byte <= (read_index < SNAPSHOT_BYTES) ? snapshot[read_index] : 8'h00;
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end
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endmodule
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