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feat: hold the WiFi module in reset until enabled by the firmware (FPGA v8)

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randogoth 2026-10-25 16:13:29 +02:00
parent eaf8cd284a
commit 853addaa22
6 changed files with 24 additions and 9 deletions
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4
tools/jitter.py
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@ -82,8 +82,8 @@ class Board:
while self.serial.readline():
pass
self.serial.timeout = 200
if not identity.startswith("STRX v7"):
sys.exit(f"unexpected board identity: {identity!r} (needs the v7 FPGA image)")
if not identity.startswith("STRX v8"):
sys.exit(f"unexpected board identity: {identity!r} (needs the v8 FPGA image)")
self.generators = self.read(REG_GENERATORS)
self.rings = self.read(REG_RINGS)
print(f"board: {identity}, {self.generators} generators x {self.rings} rings")