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feat: hold the WiFi module in reset until enabled by the firmware (FPGA v8)

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randogoth 2026-10-25 16:13:29 +02:00
parent eaf8cd284a
commit 853addaa22
6 changed files with 24 additions and 9 deletions
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5
fpga/src/strix.qsf
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@ -87,6 +87,11 @@ set_global_assignment -name CONFIGURATION_VCCIO_LEVEL AUTO
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
set_global_assignment -name GENERATE_TTF_FILE ON
# Weak pull-ups keep the NINA module's SS and GPIO0 (boot mode) high while the SAMD21 leaves
# these pass-through pins floating. Its reset is gated in the FPGA (REG_NINA_CTRL).
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bMKR_D[5]
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to bMKR_D[6]
set_location_assignment PIN_E2 -to iCLK
set_location_assignment PIN_E1 -to iRESETn
set_location_assignment PIN_E10 -to oSDRAM_ADDR[11]