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feat: hold the WiFi module in reset until enabled by the firmware (FPGA v8)

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randogoth 2026-10-25 16:13:29 +02:00
parent eaf8cd284a
commit 853addaa22
6 changed files with 24 additions and 9 deletions
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9
fpga/rtl/strix_core.v
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@ -36,10 +36,11 @@ module strix_core #(
input wire spi_mosi,
input wire spi_ss_n,
output wire spi_miso,
output wire capture_done
output wire capture_done,
output reg nina_enable // releases the WiFi module from reset (see REG_NINA_CTRL)
);
localparam [7:0] VERSION = 8'h07;
localparam [7:0] VERSION = 8'h08;
localparam GENERATORS = 4;
localparam [6:0] REG_ID0 = 7'h00, // "STRX"
@ -84,6 +85,7 @@ module strix_core #(
REG_LEVEL_LOW = 7'h2B,
REG_DROP_HIGH = 7'h2C, // bytes dropped because the FIFO was full
REG_DROP_LOW = 7'h2D,
REG_NINA_CTRL = 7'h2E, // bit 0: WiFi module may run (otherwise held in reset)
REG_STATS = 7'h40, // burst read of the statistics trial snapshot
REG_STREAM = 7'h44, // burst read of entropy bytes
REG_AMP = 7'h42, // burst read of the amplifier trial snapshot
@ -327,6 +329,7 @@ module strix_core #(
REG_LEVEL_LOW: tx_byte_next = stream_level[7:0];
REG_DROP_HIGH: tx_byte_next = stream_dropped[15:8];
REG_DROP_LOW: tx_byte_next = stream_dropped[7:0];
REG_NINA_CTRL: tx_byte_next = {7'd0, nina_enable};
REG_AMP_CTRL: tx_byte_next = {7'd0, amp_von_neumann};
REG_AMP_SOURCES: tx_byte_next = {4'd0, amp_sources};
REG_AMP_SUB_MS: tx_byte_next = amp_sub_ms;
@ -403,6 +406,7 @@ module strix_core #(
amp_stage_param <= {16'd4, 16'd8, 16'd8}; // random walk 8 x 8 x 4 = bound 256
amp_index <= 8'd0;
stream_source <= 3'd4;
nina_enable <= 1'b0;
stream_von_neumann <= 1'b0;
is_read <= 1'b0;
reg_addr <= 7'd0;
@ -450,6 +454,7 @@ module strix_core #(
REG_MAX_DEAD: max_dead <= rx_byte;
REG_TRIAL_HIGH: trial_ms[15:8] <= rx_byte;
REG_TRIAL_LOW: trial_ms[7:0] <= rx_byte;
REG_NINA_CTRL: nina_enable <= rx_byte[0];
REG_STREAM_CTRL: begin
if (rx_byte[2:0] <= 3'd4) stream_source <= rx_byte[2:0];
stream_von_neumann <= rx_byte[3];