feat: hold the WiFi module in reset until enabled by the firmware (FPGA v8)
This commit is contained in:
parent
eaf8cd284a
commit
853addaa22
6 changed files with 24 additions and 9 deletions
|
|
@ -34,6 +34,8 @@ module strix (
|
|||
|
||||
// NINA pass-through: the SAMD21 talks to the WiFi module as if wired directly.
|
||||
|
||||
wire nina_enable; // from strix_core
|
||||
|
||||
wire sam_nina_mosi = bMKR_D[8]; // SERCOM1
|
||||
wire sam_nina_sck = bMKR_D[9];
|
||||
wire sam_nina_ss = bMKR_D[5];
|
||||
|
|
@ -45,7 +47,9 @@ module strix (
|
|||
assign bWM_PIO29 = sam_nina_sck;
|
||||
assign bWM_PIO28 = sam_nina_ss;
|
||||
assign bWM_PIO27 = sam_nina_gpio0;
|
||||
assign oWM_RESET = sam_nina_resetn;
|
||||
// The module stays in reset until the firmware enables it: its boot current on top of the
|
||||
// ring oscillators can brown out the board, and it is not needed without WiFi.
|
||||
assign oWM_RESET = nina_enable ? sam_nina_resetn : 1'b0;
|
||||
assign oWM_RX = sam_uart_tx;
|
||||
assign bWM_PIO1 = 1'bz; // inputs from NINA
|
||||
assign bWM_PIO7 = 1'bz;
|
||||
|
|
@ -64,7 +68,7 @@ module strix (
|
|||
strix_core core (
|
||||
.clk(clk), .reset(reset),
|
||||
.spi_sck(strix_sck), .spi_mosi(strix_mosi), .spi_ss_n(strix_ss_n),
|
||||
.spi_miso(strix_miso), .capture_done(capture_done)
|
||||
.spi_miso(strix_miso), .capture_done(capture_done), .nina_enable(nina_enable)
|
||||
);
|
||||
|
||||
assign oSAM_INT = capture_done;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue