feat: hold the WiFi module in reset until enabled by the firmware (FPGA v8)
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6 changed files with 24 additions and 9 deletions
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@ -1,4 +1,4 @@
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// STRIX FPGA register map (FPGA version 7). Mirrors the definitions in fpga/rtl/strix_core.v,
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// STRIX FPGA register map (FPGA version 8). Mirrors the definitions in fpga/rtl/strix_core.v,
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// which also documents the SPI protocol and snapshot layouts.
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#pragma once
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@ -6,7 +6,7 @@
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namespace strix {
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const uint8_t FPGA_VERSION = 7;
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const uint8_t FPGA_VERSION = 8;
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const uint8_t READ = 0x80; // command bit 7: read
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enum Register : uint8_t {
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@ -42,6 +42,7 @@ enum Register : uint8_t {
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REG_LEVEL_LOW = 0x2B,
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REG_DROP_HIGH = 0x2C,
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REG_DROP_LOW = 0x2D,
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REG_NINA_CTRL = 0x2E, // bit 0: WiFi module may run
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REG_GEN_HEALTH = 0x30, // + 4g: flags, RCT events, APT events, dead rings
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REG_STATS = 0x40,
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REG_AMP = 0x42,
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