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feat: add entropy byte stream FIFO and faster SPI read-back (FPGA v7)

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randogoth 2026-10-25 15:29:30 +02:00
parent 8541cce59c
commit 7777384495
6 changed files with 232 additions and 38 deletions
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fpga/src/strix.qsf
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@ -63,6 +63,7 @@ set_global_assignment -name VERILOG_FILE ../rtl/strix_core.v
set_global_assignment -name VERILOG_FILE ../rtl/entropy_generator.v
set_global_assignment -name VERILOG_FILE ../rtl/health_monitor.v
set_global_assignment -name VERILOG_FILE ../rtl/stats_block.v
set_global_assignment -name VERILOG_FILE ../rtl/entropy_stream.v
set_global_assignment -name VERILOG_FILE ../rtl/bias_amplifier.v
set_global_assignment -name VERILOG_FILE ../rtl/amp_path.v
set_global_assignment -name VERILOG_FILE ../rtl/amp_stage.v