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feat: add entropy byte stream FIFO and faster SPI read-back (FPGA v7)

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randogoth 2026-10-25 15:29:30 +02:00
parent 8541cce59c
commit 7777384495
6 changed files with 232 additions and 38 deletions
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42
fpga/rtl/bias_amplifier.v
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@ -72,12 +72,13 @@ module bias_amplifier #(
reg [16:0] tick_count;
reg [7:0] ms_count;
reg [3:0] sub_index;
reg sub_end;
reg sub_end, trial_due;
wire tick = (tick_count == TICK_CYCLES - 1);
always @(posedge clk) begin
sub_end <= 1'b0;
trial_end <= 1'b0;
trial_due <= 1'b0;
trial_end <= trial_due;
if (start_over) begin
tick_count <= 17'd0;
ms_count <= 8'd0;
@ -92,11 +93,12 @@ module bias_amplifier #(
ms_count <= ms_count + 8'd1;
end
end
// trial_end follows the last sub_end by one cycle, once its vote is registered.
// trial_end follows the last sub_end by two cycles, once its vote and the vote
// counts are registered.
if (sub_end) begin
if (sub_index + 4'd1 >= subtrials) begin
sub_index <= 4'd0;
trial_end <= 1'b1;
trial_due <= 1'b1;
end else begin
sub_index <= sub_index + 4'd1;
end
@ -110,6 +112,8 @@ module bias_amplifier #(
wire [31:0] trial_ones [0:1];
wire [15:0] votes [0:1];
wire [15:0] voted [0:1];
wire [4:0] vote_count [0:1];
wire [4:0] one_votes [0:1];
wire [1:0] overflow;
amp_path #(.GENERATORS(GENERATORS)) bias_path (
@ -117,7 +121,8 @@ module bias_amplifier #(
.stage_mode(stage_mode), .stage_param(stage_param),
.sub_end(sub_end), .sub_index(sub_index), .trial_end(trial_end),
.trial_bits(trial_bits[0]), .trial_ones(trial_ones[0]),
.votes(votes[0]), .voted(voted[0]), .overflow(overflow[0])
.votes(votes[0]), .voted(voted[0]), .vote_count(vote_count[0]), .one_votes(one_votes[0]),
.overflow(overflow[0])
);
amp_path #(.GENERATORS(GENERATORS)) autocorrelation_path (
@ -125,27 +130,18 @@ module bias_amplifier #(
.stage_mode(stage_mode), .stage_param(stage_param),
.sub_end(sub_end), .sub_index(sub_index), .trial_end(trial_end),
.trial_bits(trial_bits[1]), .trial_ones(trial_ones[1]),
.votes(votes[1]), .voted(voted[1]), .overflow(overflow[1])
.votes(votes[1]), .voted(voted[1]), .vote_count(vote_count[1]), .one_votes(one_votes[1]),
.overflow(overflow[1])
);
// Snapshot
function [4:0] count_ones(input [15:0] value);
integer b;
function [127:0] path_bytes(input [31:0] bits, input [31:0] ones, input [15:0] vote, input [15:0] cast,
input [4:0] cast_count, input [4:0] ones_cast);
reg valid, result;
begin
count_ones = 5'd0;
for (b = 0; b < 16; b = b + 1) count_ones = count_ones + value[b];
end
endfunction
function [127:0] path_bytes(input [31:0] bits, input [31:0] ones, input [15:0] vote, input [15:0] cast);
reg [4:0] cast_count, one_votes;
reg valid, result;
begin
cast_count = count_ones(cast);
one_votes = count_ones(vote & cast);
valid = cast_count != 0 && {one_votes, 1'b0} != {1'b0, cast_count};
result = {one_votes, 1'b0} > {1'b0, cast_count};
valid = cast_count != 0 && {ones_cast, 1'b0} != {1'b0, cast_count};
result = {ones_cast, 1'b0} > {1'b0, cast_count};
path_bytes = {bits, ones, vote, cast, 3'd0, cast_count, 6'd0, valid, result, 16'd0};
end
endfunction
@ -159,8 +155,8 @@ module bias_amplifier #(
sequence_number,
2'd0, |overflow, von_neumann_during & von_neumann, sources_during & sources,
4'd0, subtrials, sub_ms, 8'd0,
path_bytes(trial_bits[0], trial_ones[0], votes[0], voted[0]),
path_bytes(trial_bits[1], trial_ones[1], votes[1], voted[1]),
path_bytes(trial_bits[0], trial_ones[0], votes[0], voted[0], vote_count[0], one_votes[0]),
path_bytes(trial_bits[1], trial_ones[1], votes[1], voted[1], vote_count[1], one_votes[1]),
sequence_number
};