feat: add entropy byte stream FIFO and faster SPI read-back (FPGA v7)

fpga/rtl/amp_path.v

@@ -18,6 +18,8 @@ module amp_path #(
     output reg  [31:0]           trial_ones,
     output reg  [15:0]           votes,        // bit i: sub-trial i voted 1
     output reg  [15:0]           voted,        // bit i: sub-trial i had a majority
+    output reg  [4:0]            vote_count,   // sub-trials that voted (registered from voted)
+    output reg  [4:0]            one_votes,    // of those, voted 1
     output reg                   overflow      // a merge input arrived before the last was taken
 );
 
@@ -81,6 +83,14 @@ module amp_path #(
 
     reg [23:0] sub_bits, sub_ones;
 
+    function [4:0] count_ones(input [15:0] value);
+        integer b;
+        begin
+            count_ones = 5'd0;
+            for (b = 0; b < 16; b = b + 1) count_ones = count_ones + value[b];
+        end
+    endfunction
+
     always @(posedge clk) begin
         if (restart || trial_end) begin
             trial_bits <= out_valid ? 32'd1 : 32'd0;
@@ -100,6 +110,10 @@ module amp_path #(
             sub_ones <= sub_ones + out_bit;
         end
 
+        // Registered counts, ready one cycle after the last vote of a trial
+        vote_count <= count_ones(voted);
+        one_votes  <= count_ones(votes & voted);
+
         if (!restart && sub_end && sub_bits != 0 && {sub_ones, 1'b0} != sub_bits) begin
             voted[sub_index] <= 1'b1;
             votes[sub_index] <= {sub_ones, 1'b0} > sub_bits;