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feat: add per-second GCP-format trials with history, watch and HTTP access (FPGA v10)

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randogoth 2026-10-25 18:23:18 +02:00
parent d821b77d3b
commit 6bee626b7f
12 changed files with 475 additions and 29 deletions
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fpga/src/strix.qsf
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@ -67,6 +67,7 @@ set_global_assignment -name VERILOG_FILE ../rtl/entropy_stream.v
set_global_assignment -name VERILOG_FILE ../rtl/bias_amplifier.v
set_global_assignment -name VERILOG_FILE ../rtl/amp_path.v
set_global_assignment -name VERILOG_FILE ../rtl/amp_stage.v
set_global_assignment -name VERILOG_FILE ../rtl/gcp_block.v
set_global_assignment -name VERILOG_FILE ../rtl/freq_counter.v
set_global_assignment -name VERILOG_FILE ../rtl/ring_osc.v
set_global_assignment -name VERILOG_FILE ../rtl/raw_capture.v