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feat: add per-second GCP-format trials with history, watch and HTTP access (FPGA v10)

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randogoth 2026-10-25 18:23:18 +02:00
parent d821b77d3b
commit 6bee626b7f
12 changed files with 475 additions and 29 deletions
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6
arduino/libraries/StrixFPGA/src/StrixRegisters.h
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@ -1,4 +1,4 @@
// STRIX FPGA register map (FPGA version 9). Mirrors the definitions in fpga/rtl/strix_core.v,
// STRIX FPGA register map (FPGA version 10). Mirrors the definitions in fpga/rtl/strix_core.v,
// which also documents the SPI protocol and snapshot layouts.
#pragma once
@ -6,7 +6,7 @@
namespace strix {
const uint8_t FPGA_VERSION = 9;
const uint8_t FPGA_VERSION = 10;
const uint8_t READ = 0x80; // command bit 7: read
enum Register : uint8_t {
@ -47,6 +47,7 @@ enum Register : uint8_t {
REG_STATS = 0x40,
REG_AMP = 0x42,
REG_STREAM = 0x44,
REG_GCP = 0x46,
REG_AMP_CTRL = 0x50,
REG_AMP_SOURCES = 0x51,
REG_AMP_SUB_MS = 0x52,
@ -71,6 +72,7 @@ const uint8_t GENERATORS = 4;
const uint8_t STATS_CHANNELS = GENERATORS + 1; // generators, then the combined channel
const uint8_t STATS_SNAPSHOT_BYTES = 72;
const uint8_t AMP_SNAPSHOT_BYTES = 44;
const uint8_t GCP_SNAPSHOT_BYTES = 36;
const size_t CAPTURE_BYTES = 32768;
} // namespace strix