feat: add per-generator NIST health tests and dead-ring monitor, onod3000 output test (FPGA v4)
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randogoth
parent
585e755c66
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67bd7eec58
9 changed files with 436 additions and 28 deletions
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@ -1,5 +1,5 @@
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// Board-independent STRIX logic: entropy generators, source selection, raw capture,
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// frequency counter and the SPI register interface to the SAMD21.
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// Board-independent STRIX logic: entropy generators with health monitors, source selection,
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// raw capture, frequency counter and the SPI register interface to the SAMD21.
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//
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// SPI protocol (mode 0, one transaction per ss_n low period): the first byte is a command,
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// bit 7 = read (1) or write (0), bits 6:0 = register address. A write stores the following
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@ -11,10 +11,15 @@
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// 0x04+g spatial XOR of all rings, every clock
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// 0x08+g enhanced output of ring RING_SELECT
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// 0x0C+g single tap of ring RING_SELECT
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//
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// Health: a generator is healthy when it is enabled, its monitor has completed a dead-ring
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// sweep, neither NIST test has failed since the last clear, and at most MAX_DEAD_RINGS rings
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// are dead. Per-generator registers at 0x30 + 4g: FLAGS, RCT_EVENTS, APT_EVENTS, DEAD_RINGS.
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module strix_core #(
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parameter CAPTURE_ADDR_WIDTH = 15,
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parameter FREQ_GATE_BITS = 24,
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parameter RINGS_PER_GEN = 90
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parameter RINGS_PER_GEN = 90,
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parameter DEAD_WINDOW_BITS = 16
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) (
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input wire clk,
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input wire reset,
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@ -25,7 +30,7 @@ module strix_core #(
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output wire capture_done
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);
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localparam [7:0] VERSION = 8'h03;
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localparam [7:0] VERSION = 8'h04;
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localparam GENERATORS = 4;
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localparam [6:0] REG_ID0 = 7'h00, // "STRX"
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@ -53,7 +58,20 @@ module strix_core #(
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REG_FREQ_COUNT0 = 7'h15,
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REG_GEN_ENABLE = 7'h16, // bit g enables generator g
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REG_TEMPORAL = 7'h17, // consecutive bits XORed per output bit, 1-8
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REG_FREQ_GEN = 7'h18; // generator for the frequency measurement
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REG_FREQ_GEN = 7'h18, // generator for the frequency measurement
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REG_HEALTHY = 7'h20, // read-only: bit g = generator g healthy
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REG_HEALTH_CTRL = 7'h21, // write: bit 0 clears failures and event counters
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REG_RCT_CUTOFF = 7'h22, // repetition count test cutoff (run length)
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REG_APT_HIGH = 7'h23, // adaptive proportion test cutoff (per 1024 bits)
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REG_APT_LOW = 7'h24,
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REG_MAX_DEAD = 7'h25; // dead rings tolerated per generator
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// Per-generator health registers at 0x30 + 4g + index
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localparam [1:0] GEN_FLAGS = 2'd0, // bit 0 RCT failed, 1 APT failed, 2 too many dead rings,
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// 3 active, 4 sweep done, 5 healthy
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GEN_RCT_EVENTS = 2'd1,
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GEN_APT_EVENTS = 2'd2,
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GEN_DEAD_RINGS = 2'd3;
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// Generators
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@ -62,15 +80,39 @@ module strix_core #(
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reg [7:0] ring_select;
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wire [GENERATORS-1:0] out_bit, spatial_bit, ring_enhanced, ring_tap, ring_raw_tap;
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reg health_clear;
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reg [7:0] rct_cutoff, max_dead;
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reg [10:0] apt_cutoff;
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wire [GENERATORS-1:0] rct_failed, apt_failed, sweep_done, too_many_dead, healthy;
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wire [7:0] rct_events [0:GENERATORS-1];
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wire [7:0] apt_events [0:GENERATORS-1];
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wire [7:0] dead_rings [0:GENERATORS-1];
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genvar g;
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generate
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for (g = 0; g < GENERATORS; g = g + 1) begin : gen
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wire [RINGS_PER_GEN-1:0] ring_samples;
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wire active = gen_enable[g] && !reset;
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entropy_generator #(.RINGS(RINGS_PER_GEN)) generator (
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.clk(clk), .enable(gen_enable[g]), .temporal(temporal), .ring_select(ring_select),
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.out_bit(out_bit[g]), .spatial_bit(spatial_bit[g]),
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.ring_enhanced(ring_enhanced[g]), .ring_tap(ring_tap[g]),
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.ring_raw_tap(ring_raw_tap[g])
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.ring_raw_tap(ring_raw_tap[g]), .ring_samples(ring_samples)
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);
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health_monitor #(.RINGS(RINGS_PER_GEN), .DEAD_WINDOW_BITS(DEAD_WINDOW_BITS)) monitor (
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.clk(clk), .active(active), .clear(health_clear),
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.sample_bit(spatial_bit[g]), .ring_samples(ring_samples),
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.rct_cutoff(rct_cutoff), .apt_cutoff(apt_cutoff),
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.rct_failed(rct_failed[g]), .apt_failed(apt_failed[g]),
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.rct_events(rct_events[g]), .apt_events(apt_events[g]),
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.dead_rings(dead_rings[g]), .sweep_done(sweep_done[g])
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);
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assign too_many_dead[g] = sweep_done[g] && dead_rings[g] > max_dead;
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assign healthy[g] = active && sweep_done[g] && !rct_failed[g] && !apt_failed[g]
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&& !too_many_dead[g];
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end
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endgenerate
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@ -136,6 +178,22 @@ module strix_core #(
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wire reading_data = is_read && reg_addr == REG_DATA;
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function [7:0] gen_register(input [6:0] addr);
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reg [1:0] n;
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begin
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n = addr[3:2];
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if (addr[6:4] != 3'b011)
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gen_register = 8'h00;
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else case (addr[1:0])
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GEN_FLAGS: gen_register = {2'd0, healthy[n], sweep_done[n], gen_enable[n],
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too_many_dead[n], apt_failed[n], rct_failed[n]};
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GEN_RCT_EVENTS: gen_register = rct_events[n];
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GEN_APT_EVENTS: gen_register = apt_events[n];
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default: gen_register = sweep_done[n] ? dead_rings[n] : 8'h00;
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endcase
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end
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endfunction
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always @(*) begin
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case (reg_addr)
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REG_ID0: tx_byte = "S";
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@ -161,13 +219,19 @@ module strix_core #(
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REG_GEN_ENABLE: tx_byte = {4'd0, gen_enable};
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REG_TEMPORAL: tx_byte = {4'd0, temporal};
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REG_FREQ_GEN: tx_byte = {6'd0, freq_gen};
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default: tx_byte = 8'h00;
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REG_HEALTHY: tx_byte = {4'd0, healthy};
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REG_RCT_CUTOFF: tx_byte = rct_cutoff;
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REG_APT_HIGH: tx_byte = {5'd0, apt_cutoff[10:8]};
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REG_APT_LOW: tx_byte = apt_cutoff[7:0];
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REG_MAX_DEAD: tx_byte = max_dead;
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default: tx_byte = gen_register(reg_addr);
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endcase
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end
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always @(posedge clk) begin
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capture_start <= 1'b0;
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freq_start <= 1'b0;
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health_clear <= 1'b0;
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if (reset) begin
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gen_enable <= {GENERATORS{1'b1}};
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temporal <= 4'd5;
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@ -177,6 +241,10 @@ module strix_core #(
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pair_mode <= 1'b0;
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decimation <= 16'd5;
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freq_gen <= 2'd0;
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rct_cutoff <= 8'd81; // 0.5 bits/bit claimed, alpha 2^-40
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apt_cutoff <= 11'd824; // same, 1024-bit window
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max_dead <= 8'd8; // measured sizing tolerates about 17
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health_clear <= 1'b1;
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is_read <= 1'b0;
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reg_addr <= 7'd0;
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bytes_read <= {CAPTURE_ADDR_WIDTH{1'b0}};
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@ -204,6 +272,11 @@ module strix_core #(
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REG_GEN_ENABLE: gen_enable <= rx_byte[GENERATORS-1:0];
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REG_TEMPORAL: if (rx_byte >= 8'd1 && rx_byte <= 8'd8) temporal <= rx_byte[3:0];
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REG_FREQ_GEN: freq_gen <= rx_byte[1:0];
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REG_HEALTH_CTRL: health_clear <= rx_byte[0];
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REG_RCT_CUTOFF: if (rx_byte >= 8'd2) rct_cutoff <= rx_byte;
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REG_APT_HIGH: apt_cutoff[10:8] <= rx_byte[2:0];
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REG_APT_LOW: apt_cutoff[7:0] <= rx_byte;
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REG_MAX_DEAD: max_dead <= rx_byte;
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REG_CONTROL: begin
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if (rx_byte[0]) capture_start <= 1'b1;
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if (rx_byte[0] || rx_byte[1]) bytes_read <= {CAPTURE_ADDR_WIDTH{1'b0}};
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