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fix: hand GPIO0 to the WiFi module, count only healthy generators, shorten amplifier stage path (FPGA v9)

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randogoth 2026-10-25 16:13:41 +02:00
parent 2a96333aef
commit 5c69d826a2
7 changed files with 61 additions and 31 deletions
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4
tools/jitter.py
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@ -82,8 +82,8 @@ class Board:
while self.serial.readline():
pass
self.serial.timeout = 200
if not identity.startswith("STRX v8"):
sys.exit(f"unexpected board identity: {identity!r} (needs the v8 FPGA image)")
if not identity.startswith("STRX v9"):
sys.exit(f"unexpected board identity: {identity!r} (needs the v9 FPGA image)")
self.generators = self.read(REG_GENERATORS)
self.rings = self.read(REG_RINGS)
print(f"board: {identity}, {self.generators} generators x {self.rings} rings")