randogoth/strix
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

fix: hand GPIO0 to the WiFi module, count only healthy generators, shorten amplifier stage path (FPGA v9)

Browse source
This commit is contained in:
randogoth 2026-10-25 16:13:41 +02:00
parent 2a96333aef
commit 5c69d826a2
7 changed files with 61 additions and 31 deletions
Download patch file Download diff file Expand all files Collapse all files

22
fpga/rtl/strix_core.v
View file

@ -37,10 +37,11 @@ module strix_core #(
input wire spi_ss_n,
output wire spi_miso,
output wire capture_done,
output reg nina_enable // releases the WiFi module from reset (see REG_NINA_CTRL)
output reg nina_enable, // releases the WiFi module from reset (see REG_NINA_CTRL)
output reg nina_gpio0_in // GPIO0 is driven by the module (to the SAMD21), not to it
);
localparam [7:0] VERSION = 8'h08;
localparam [7:0] VERSION = 8'h09;
localparam GENERATORS = 4;
localparam [6:0] REG_ID0 = 7'h00, // "STRX"
@ -85,7 +86,10 @@ module strix_core #(
REG_LEVEL_LOW = 7'h2B,
REG_DROP_HIGH = 7'h2C, // bytes dropped because the FIFO was full
REG_DROP_LOW = 7'h2D,
REG_NINA_CTRL = 7'h2E, // bit 0: WiFi module may run (otherwise held in reset)
REG_NINA_CTRL = 7'h2E, // bit 0: WiFi module may run (otherwise held in reset);
// bit 1: GPIO0 direction, 0 SAMD21 -> module (boot
// mode selection), 1 module -> SAMD21 (its data-ready
// signal once running)
REG_STATS = 7'h40, // burst read of the statistics trial snapshot
REG_STREAM = 7'h44, // burst read of entropy bytes
REG_AMP = 7'h42, // burst read of the amplifier trial snapshot
@ -208,7 +212,9 @@ module strix_core #(
);
stats_block #(.CHANNELS(GENERATORS + 1), .TICK_CYCLES(TICK_CYCLES)) stats (
.clk(clk), .reset(reset), .bits(stats_bits), .valid(stats_valid),
// Only healthy generators are counted; the combined channel while any is healthy.
.clk(clk), .reset(reset), .bits(stats_bits),
.valid({GENERATORS + 1{stats_valid}} & {|stats_healthy, stats_healthy}),
.von_neumann(stats_von_neumann), .trial_ms(trial_ms), .restart(stats_restart),
.healthy(stats_healthy), .read_index(stats_index), .read_byte(stats_byte),
.trial_end(trial_end)
@ -329,7 +335,7 @@ module strix_core #(
REG_LEVEL_LOW: tx_byte_next = stream_level[7:0];
REG_DROP_HIGH: tx_byte_next = stream_dropped[15:8];
REG_DROP_LOW: tx_byte_next = stream_dropped[7:0];
REG_NINA_CTRL: tx_byte_next = {7'd0, nina_enable};
REG_NINA_CTRL: tx_byte_next = {6'd0, nina_gpio0_in, nina_enable};
REG_AMP_CTRL: tx_byte_next = {7'd0, amp_von_neumann};
REG_AMP_SOURCES: tx_byte_next = {4'd0, amp_sources};
REG_AMP_SUB_MS: tx_byte_next = amp_sub_ms;
@ -407,6 +413,7 @@ module strix_core #(
amp_index <= 8'd0;
stream_source <= 3'd4;
nina_enable <= 1'b0;
nina_gpio0_in <= 1'b0;
stream_von_neumann <= 1'b0;
is_read <= 1'b0;
reg_addr <= 7'd0;
@ -454,7 +461,10 @@ module strix_core #(
REG_MAX_DEAD: max_dead <= rx_byte;
REG_TRIAL_HIGH: trial_ms[15:8] <= rx_byte;
REG_TRIAL_LOW: trial_ms[7:0] <= rx_byte;
REG_NINA_CTRL: nina_enable <= rx_byte[0];
REG_NINA_CTRL: begin
nina_enable <= rx_byte[0];
nina_gpio0_in <= rx_byte[1];
end
REG_STREAM_CTRL: begin
if (rx_byte[2:0] <= 3'd4) stream_source <= rx_byte[2:0];
stream_von_neumann <= rx_byte[3];