fix: hand GPIO0 to the WiFi module, count only healthy generators, shorten amplifier stage path (FPGA v9)

fpga/rtl/strix.v

@@ -34,7 +34,7 @@ module strix (
 
     // NINA pass-through: the SAMD21 talks to the WiFi module as if wired directly.
 
-    wire nina_enable;  // from strix_core
+    wire nina_enable, nina_gpio0_in;  // from strix_core
 
     wire sam_nina_mosi   = bMKR_D[8];   // SERCOM1
     wire sam_nina_sck    = bMKR_D[9];
@@ -46,7 +46,9 @@ module strix (
     assign bWM_PIO36 = sam_nina_mosi;
     assign bWM_PIO29 = sam_nina_sck;
     assign bWM_PIO28 = sam_nina_ss;
-    assign bWM_PIO27 = sam_nina_gpio0;
+    // GPIO0 is bidirectional on the module: the SAMD21 drives it to select the boot mode, the
+    // running module drives it as its data-ready signal. Only one side drives at a time.
+    assign bWM_PIO27 = nina_gpio0_in ? 1'bz : sam_nina_gpio0;
     // The module stays in reset until the firmware enables it: its boot current on top of the
     // ring oscillators can brown out the board, and it is not needed without WiFi.
     assign oWM_RESET = nina_enable ? sam_nina_resetn : 1'b0;
@@ -57,6 +59,7 @@ module strix (
     wire nina_miso    = bWM_PIO1;       // to D10
     wire nina_ack     = bWM_PIO7;       // to D4
     wire nina_uart_tx = iWM_TX;         // to D13
+    wire nina_gpio0   = bWM_PIO27;      // to D6 while the module drives it
 
     // STRIX SPI link on SAMD21 SERCOM0 alternate pins: A3 MOSI, A4 SCK, A5 SS, A6 MISO.
 
@@ -68,7 +71,8 @@ module strix (
     strix_core core (
         .clk(clk), .reset(reset),
         .spi_sck(strix_sck), .spi_mosi(strix_mosi), .spi_ss_n(strix_ss_n),
-        .spi_miso(strix_miso), .capture_done(capture_done), .nina_enable(nina_enable)
+        .spi_miso(strix_miso), .capture_done(capture_done), .nina_enable(nina_enable),
+        .nina_gpio0_in(nina_gpio0_in)
     );
 
     assign oSAM_INT = capture_done;
@@ -79,6 +83,7 @@ module strix (
     generate
         for (d = 0; d < 15; d = d + 1) begin : header_d
             assign bMKR_D[d] = (d == 4)  ? nina_ack :
+                               (d == 6)  ? (nina_gpio0_in ? nina_gpio0 : 1'bz) :
                                (d == 10) ? nina_miso :
                                (d == 13) ? nina_uart_tx : 1'bz;
         end