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fix: hand GPIO0 to the WiFi module, count only healthy generators, shorten amplifier stage path (FPGA v9)

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randogoth 2026-10-25 16:13:41 +02:00
parent 2a96333aef
commit 5c69d826a2
7 changed files with 61 additions and 31 deletions
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17
fpga/rtl/stats_block.v
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@ -23,7 +23,7 @@ module stats_block #(
input wire clk,
input wire reset,
input wire [CHANNELS-1:0] bits,
input wire valid, // new bits on all channels this cycle
input wire [CHANNELS-1:0] valid, // new bit on each channel this cycle
input wire von_neumann,
input wire [15:0] trial_ms,
input wire restart, // start a new trial now, sequence back to 0
@ -61,17 +61,20 @@ module stats_block #(
// Von Neumann extraction per channel
reg [CHANNELS-1:0] pair_first, have_first;
wire [CHANNELS-1:0] vn_valid = have_first & (bits ^ pair_first);
wire [CHANNELS-1:0] count_valid = von_neumann ? (valid ? vn_valid : {CHANNELS{1'b0}})
: {CHANNELS{valid}};
wire [CHANNELS-1:0] vn_valid = valid & have_first & (bits ^ pair_first);
wire [CHANNELS-1:0] count_valid = von_neumann ? vn_valid : valid;
wire [CHANNELS-1:0] count_bit = von_neumann ? pair_first : bits;
integer v;
always @(posedge clk) begin
if (reset || !von_neumann) begin
have_first <= {CHANNELS{1'b0}};
end else if (valid) begin
have_first <= ~have_first;
pair_first <= bits;
end else begin
for (v = 0; v < CHANNELS; v = v + 1)
if (valid[v]) begin
have_first[v] <= ~have_first[v];
pair_first[v] <= bits[v];
end
end
end