feat: add four 90-ring entropy generators with spatial and temporal XOR (FPGA v3)

fpga/rtl/raw_capture.v

@@ -66,9 +66,13 @@ module raw_capture #(
         end
     end
 
+    // Two read registers: the first becomes the RAM's address register, the second its output
+    // register, which keeps the wide block-RAM output multiplexer off the SPI timing path.
+    reg [7:0] read_data_ram;
     always @(posedge clk) begin
         if (write_enable) buffer[write_addr] <= write_data;
-        read_data <= buffer[read_addr];
+        read_data_ram <= buffer[read_addr];
+        read_data     <= read_data_ram;
     end
 
 endmodule