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feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)

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randogoth 2026-10-25 12:56:54 +02:00
parent d51a6c0ca8
commit 504b00752a
12 changed files with 654 additions and 347 deletions
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29
fpga/rtl/raw_capture.v
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@ -1,12 +1,15 @@
// Captures one burst of sampled bits into block RAM for offline analysis. Keeps every
// decimation-th sample of the selected source and packs them MSB first into bytes.
// decimation-th sample and packs it MSB first into bytes: one bit per sample from
// source A, or in pair mode two bits per sample (A then B) so both sources are recorded
// at the same instants.
module raw_capture #(
parameter ADDR_WIDTH = 15 // 2^15 bytes = 256 Kbit per burst
) (
input wire clk,
input wire reset,
input wire [3:0] samples,
input wire [1:0] source,
input wire bit_a,
input wire bit_b,
input wire pair_mode,
input wire [15:0] decimation, // 0 and 1 both mean every sample
input wire start,
output reg busy,
@ -18,8 +21,8 @@ module raw_capture #(
reg [7:0] buffer [0:(1 << ADDR_WIDTH) - 1];
reg [15:0] sample_count;
reg [2:0] bit_count;
reg [6:0] partial_byte;
reg [3:0] bit_count;
reg [7:0] partial_byte;
reg [ADDR_WIDTH-1:0] next_addr;
reg write_enable;
reg [ADDR_WIDTH-1:0] write_addr;
@ -27,7 +30,9 @@ module raw_capture #(
wire keep_sample = (sample_count == 16'd0);
wire count_wraps = (decimation <= 16'd1) || (sample_count == decimation - 16'd1);
wire new_bit = samples[source];
wire [7:0] shifted = pair_mode ? {partial_byte[5:0], bit_a, bit_b} : {partial_byte[6:0], bit_a};
wire [3:0] new_count = bit_count + (pair_mode ? 4'd2 : 4'd1);
always @(posedge clk) begin
write_enable <= 1'b0;
@ -38,22 +43,24 @@ module raw_capture #(
busy <= 1'b1;
done <= 1'b0;
sample_count <= 16'd0;
bit_count <= 3'd0;
bit_count <= 4'd0;
next_addr <= {ADDR_WIDTH{1'b0}};
end else if (busy) begin
sample_count <= count_wraps ? 16'd0 : sample_count + 16'd1;
if (keep_sample) begin
partial_byte <= {partial_byte[5:0], new_bit};
bit_count <= bit_count + 3'd1;
if (bit_count == 3'd7) begin
partial_byte <= shifted;
if (new_count == 4'd8) begin
bit_count <= 4'd0;
write_enable <= 1'b1;
write_addr <= next_addr;
write_data <= {partial_byte, new_bit};
write_data <= shifted;
next_addr <= next_addr + 1'b1;
if (&next_addr) begin
busy <= 1'b0;
done <= 1'b1;
end
end else begin
bit_count <= new_count;
end
end
end