feat: add 16-ring bank, sampled XOR, pair capture and frequency counter (FPGA v2)

devbox.json

@@ -23,7 +23,7 @@
       ],
       "sim": [
         "mkdir -p /tmp/strix-sim",
-        "iverilog -g2005 -DSIM -o /tmp/strix-sim/tb_strix_core fpga/sim/tb_strix_core.v fpga/rtl/strix_core.v fpga/rtl/entropy_gen.v fpga/rtl/ring_osc.v fpga/rtl/raw_capture.v fpga/rtl/spi_slave.v",
+        "iverilog -g2005 -DSIM -o /tmp/strix-sim/tb_strix_core fpga/sim/tb_strix_core.v fpga/rtl/strix_core.v fpga/rtl/ring_bank.v fpga/rtl/freq_counter.v fpga/rtl/ring_osc.v fpga/rtl/raw_capture.v fpga/rtl/spi_slave.v",
         "vvp -n /tmp/strix-sim/tb_strix_core"
       ],
       "fpga": [
@@ -38,8 +38,8 @@
       "upload-capture": [
         "arduino-cli upload --fqbn arduino:samd:mkrvidor4000 -p ${PORT:-/dev/ttyACM0} arduino/strix_capture"
       ],
-      "capture": [
-        "python3 tools/capture.py --port ${PORT:-/dev/ttyACM0} --out captures"
+      "jitter": [
+        "python3 tools/jitter.py --port ${PORT:-/dev/ttyACM0} --out captures \"$@\""
       ]
     }
   }