diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..055a0a8 --- /dev/null +++ b/.gitignore @@ -0,0 +1,18 @@ +# Quartus build artifacts and workspace state +fpga/**/db/ +fpga/**/incremental_db/ +fpga/**/output_files/ +fpga/**/simulation/ +*.qws +*.qsf.bak +*.qarlog +*.rpt +*.summary +*.smsg +*.done +*.jdi +*.pin +*.sld + +# Devbox +.devbox/ diff --git a/devbox.json b/devbox.json new file mode 100644 index 0000000..88cd77a --- /dev/null +++ b/devbox.json @@ -0,0 +1,19 @@ +{ + "$schema": "https://raw.githubusercontent.com/jetify-com/devbox/0.17.2/.schema/devbox.schema.json", + "packages": ["arduino-cli@latest"], + "shell": { + "init_hook": [ + "echo 'Welcome to devbox!' > /dev/null" + ], + "scripts": { + "setup": [ + "arduino-cli core update-index", + "arduino-cli core install arduino:samd", + "arduino-cli lib install VidorPeripherals WiFiNINA@1.8.5" + ], + "build": [ + "arduino-cli compile --fqbn arduino:samd:mkrvidor4000 arduino/strix" + ] + } + } +} diff --git a/devbox.lock b/devbox.lock new file mode 100644 index 0000000..1ed5a06 --- /dev/null +++ b/devbox.lock @@ -0,0 +1,57 @@ +{ + "lockfile_version": "1", + "packages": { + "arduino-cli@latest": { + "last_modified": "2026-10-02T22:55:44Z", + "resolved": "github:NixOS/nixpkgs/55ba7f49ef2962b42cbd126522b7df5f95037679#arduino-cli", + "source": "devbox-search", + "version": "1.5.1", + "systems": { + "aarch64-darwin": { + "outputs": [ + { + "name": "out", + "path": "/nix/store/fk0l0iab4c2sj0p6g8yzddl47y3rwiq0-arduino-cli-1.5.1", + "default": true + } + ], + "store_path": "/nix/store/fk0l0iab4c2sj0p6g8yzddl47y3rwiq0-arduino-cli-1.5.1" + }, + "aarch64-linux": { + "outputs": [ + { + "name": "out", + "path": "/nix/store/3r1x6z5skkaf4mlvg84haqnh156cxp7c-arduino-cli-1.5.1", + "default": true + } + ], + "store_path": "/nix/store/3r1x6z5skkaf4mlvg84haqnh156cxp7c-arduino-cli-1.5.1" + }, + "x86_64-darwin": { + "outputs": [ + { + "name": "out", + "path": "/nix/store/v7qr4jwn0ibqzyqi3xqqbq20jg6d3sd5-arduino-cli-1.5.1", + "default": true + } + ], + "store_path": "/nix/store/v7qr4jwn0ibqzyqi3xqqbq20jg6d3sd5-arduino-cli-1.5.1" + }, + "x86_64-linux": { + "outputs": [ + { + "name": "out", + "path": "/nix/store/gsxcnz0k6h3hy2wb9zhdri8c6ml62arx-arduino-cli-1.5.1", + "default": true + } + ], + "store_path": "/nix/store/gsxcnz0k6h3hy2wb9zhdri8c6ml62arx-arduino-cli-1.5.1" + } + } + }, + "github:NixOS/nixpkgs/nixpkgs-unstable": { + "last_modified": "2026-09-29T03:29:29Z", + "resolved": "github:NixOS/nixpkgs/b6c8664de9b6cc07fe5666a29f91884ba81197c4?lastModified=1790652569&narHash=sha256-641r7xrlSOHYoktL9%2FaArPIYNgZJ9eM5URzSEOtPJDY%3D" + } + } +} diff --git a/fpga/src/db/strix.db_info b/fpga/src/db/strix.db_info deleted file mode 100644 index c28fcd3..0000000 --- a/fpga/src/db/strix.db_info +++ /dev/null @@ -1,3 +0,0 @@ -Quartus_Version = Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition -Version_Index = 570679552 -Creation_Time = Sun Jul 21 18:35:17 2024 diff --git a/fpga/src/db/strix.pplq.rdb b/fpga/src/db/strix.pplq.rdb deleted file mode 100644 index 7697508..0000000 Binary files a/fpga/src/db/strix.pplq.rdb and /dev/null differ diff --git a/fpga/src/db/strix.sld_design_entry.sci b/fpga/src/db/strix.sld_design_entry.sci deleted file mode 100644 index adb011c..0000000 Binary files a/fpga/src/db/strix.sld_design_entry.sci and /dev/null differ diff --git a/fpga/src/strix.qsf.bak b/fpga/src/strix.qsf.bak deleted file mode 100644 index 75ba465..0000000 --- a/fpga/src/strix.qsf.bak +++ /dev/null @@ -1,275 +0,0 @@ -# -------------------------------------------------------------------------- # -# -# Copyright (C) 2024 Intel Corporation. All rights reserved. -# Your use of Intel Corporation's design tools, logic functions -# and other software and tools, and any partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Intel Program License -# Subscription Agreement, the Intel Quartus Prime License Agreement, -# the Intel FPGA IP License Agreement, or other applicable license -# agreement, including, without limitation, that your use is for -# the sole purpose of programming logic devices manufactured by -# Intel and sold by Intel or its authorized distributors. Please -# refer to the applicable agreement for further details, at -# https://fpgasoftware.intel.com/eula. -# -# -------------------------------------------------------------------------- # -# -# Quartus Prime -# Version 23.1std.1 Build 993 05/14/2024 SC Lite Edition -# Date created = 18:01:00 July 21, 2024 -# -# -------------------------------------------------------------------------- # -# -# Notes: -# -# 1) The default values for assignments are stored in the file: -# strix_assignment_defaults.qdf -# If this file doesn't exist, see file: -# assignment_defaults.qdf -# -# 2) Intel recommends that you do not modify this file. This -# file is updated automatically by the Quartus Prime software -# and any changes you make may be lost or overwritten. -# -# -------------------------------------------------------------------------- # - - -set_global_assignment -name FAMILY "Cyclone 10 LP" -set_global_assignment -name DEVICE 10CL016YU256C8G -set_global_assignment -name TOP_LEVEL_ENTITY strix -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 23.1STD.1 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:01:00 JULY 21, 2024" -set_global_assignment -name LAST_QUARTUS_VERSION "23.1std.1 Lite Edition" -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V -set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (Verilog)" -set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity -set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan -set_location_assignment PIN_E2 -to iCLK -set_location_assignment PIN_E1 -to iRESETn -set_location_assignment PIN_E10 -to oSDRAM_ADDR[11] -set_location_assignment PIN_B13 -to oSDRAM_ADDR[10] -set_location_assignment PIN_C9 -to oSDRAM_ADDR[9] -set_location_assignment PIN_E11 -to oSDRAM_ADDR[8] -set_location_assignment PIN_D12 -to oSDRAM_ADDR[7] -set_location_assignment PIN_D11 -to oSDRAM_ADDR[6] -set_location_assignment PIN_C14 -to oSDRAM_ADDR[5] -set_location_assignment PIN_D14 -to oSDRAM_ADDR[4] -set_location_assignment PIN_A14 -to oSDRAM_ADDR[3] -set_location_assignment PIN_A15 -to oSDRAM_ADDR[2] -set_location_assignment PIN_B12 -to oSDRAM_ADDR[1] -set_location_assignment PIN_A12 -to oSDRAM_ADDR[0] -set_location_assignment PIN_B10 -to oSDRAM_BA[1] -set_location_assignment PIN_A10 -to oSDRAM_BA[0] -set_location_assignment PIN_B7 -to oSDRAM_CASn -set_location_assignment PIN_E9 -to oSDRAM_CKE -set_location_assignment PIN_A11 -to oSDRAM_CSn -set_location_assignment PIN_B6 -to bSDRAM_DQ[15] -set_location_assignment PIN_D6 -to bSDRAM_DQ[14] -set_location_assignment PIN_D8 -to bSDRAM_DQ[13] -set_location_assignment PIN_E6 -to bSDRAM_DQ[12] -set_location_assignment PIN_E8 -to bSDRAM_DQ[11] -set_location_assignment PIN_E7 -to bSDRAM_DQ[10] -set_location_assignment PIN_C8 -to bSDRAM_DQ[9] -set_location_assignment PIN_F8 -to bSDRAM_DQ[8] -set_location_assignment PIN_A6 -to bSDRAM_DQ[7] -set_location_assignment PIN_B5 -to bSDRAM_DQ[6] -set_location_assignment PIN_A5 -to bSDRAM_DQ[5] -set_location_assignment PIN_A4 -to bSDRAM_DQ[4] -set_location_assignment PIN_A3 -to bSDRAM_DQ[3] -set_location_assignment PIN_B3 -to bSDRAM_DQ[2] -set_location_assignment PIN_B4 -to bSDRAM_DQ[1] -set_location_assignment PIN_A2 -to bSDRAM_DQ[0] -set_location_assignment PIN_F9 -to oSDRAM_DQM[1] -set_location_assignment PIN_A7 -to oSDRAM_DQM[0] -set_location_assignment PIN_D9 -to oSDRAM_RASn -set_location_assignment PIN_B14 -to oSDRAM_CLK -set_location_assignment PIN_B11 -to oSDRAM_WEn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[14] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[13] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[12] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to bSDRAM_DQ[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[11] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[10] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[9] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[8] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[7] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[6] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[5] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[4] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[3] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[2] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_ADDR[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_BA[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_BA[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_CASn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_CKE -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_CLK -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_CSn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_DQM[1] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_DQM[0] -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_RASn -set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to oSDRAM_WEn -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM* -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[11] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[10] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[9] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[8] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[7] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[6] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[5] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[4] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[3] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[2] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_ADDR[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_BA[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_BA[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_DQM[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_DQM[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_RASn -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_CASn -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_WEn -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_CSn -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to oSDRAM_CKE -set_location_assignment PIN_B1 -to bMKR_AREF -set_location_assignment PIN_C2 -to bMKR_A[0] -set_location_assignment PIN_C3 -to bMKR_A[1] -set_location_assignment PIN_C6 -to bMKR_A[2] -set_location_assignment PIN_D1 -to bMKR_A[3] -set_location_assignment PIN_D3 -to bMKR_A[4] -set_location_assignment PIN_F3 -to bMKR_A[5] -set_location_assignment PIN_G2 -to bMKR_A[6] -set_location_assignment PIN_G1 -to bMKR_D[0] -set_location_assignment PIN_N3 -to bMKR_D[1] -set_location_assignment PIN_P3 -to bMKR_D[2] -set_location_assignment PIN_R3 -to bMKR_D[3] -set_location_assignment PIN_T3 -to bMKR_D[4] -set_location_assignment PIN_T2 -to bMKR_D[5] -set_location_assignment PIN_G16 -to bMKR_D[6] -set_location_assignment PIN_G15 -to bMKR_D[7] -set_location_assignment PIN_F16 -to bMKR_D[8] -set_location_assignment PIN_F15 -to bMKR_D[9] -set_location_assignment PIN_C16 -to bMKR_D[10] -set_location_assignment PIN_C15 -to bMKR_D[11] -set_location_assignment PIN_B16 -to bMKR_D[12] -set_location_assignment PIN_C11 -to bMKR_D[13] -set_location_assignment PIN_A13 -to bMKR_D[14] -set_location_assignment PIN_P8 -to bPEX_PIN6 -set_location_assignment PIN_L7 -to bPEX_PIN8 -set_location_assignment PIN_N8 -to bPEX_PIN10 -set_location_assignment PIN_T8 -to iPEX_PIN11 -set_location_assignment PIN_M8 -to bPEX_PIN12 -set_location_assignment PIN_R8 -to iPEX_PIN13 -set_location_assignment PIN_L8 -to bPEX_PIN14 -set_location_assignment PIN_M10 -to bPEX_PIN16 -set_location_assignment PIN_N12 -to bPEX_PIN20 -set_location_assignment PIN_T9 -to iPEX_PIN23 -set_location_assignment PIN_R9 -to iPEX_PIN25 -set_location_assignment PIN_T13 -to bPEX_PIN28 -set_location_assignment PIN_R12 -to bPEX_PIN30 -set_location_assignment PIN_A9 -to iPEX_PIN31 -set_location_assignment PIN_F13 -to bPEX_PIN32 -set_location_assignment PIN_B9 -to iPEX_PIN33 -set_location_assignment PIN_R13 -to bPEX_PIN42 -set_location_assignment PIN_P14 -to bPEX_PIN44 -set_location_assignment PIN_T15 -to bPEX_PIN45 -set_location_assignment PIN_R14 -to bPEX_PIN46 -set_location_assignment PIN_T14 -to bPEX_PIN47 -set_location_assignment PIN_F14 -to bPEX_PIN48 -set_location_assignment PIN_D16 -to bPEX_PIN49 -set_location_assignment PIN_D15 -to bPEX_PIN51 -set_location_assignment PIN_T12 -to bPEX_RST -set_location_assignment PIN_J13 -to iWM_PIO32 -set_location_assignment PIN_T11 -to bWM_PIO1 -set_location_assignment PIN_R10 -to bWM_PIO2 -set_location_assignment PIN_P11 -to bWM_PIO3 -set_location_assignment PIN_R11 -to bWM_PIO4 -set_location_assignment PIN_N6 -to bWM_PIO5 -set_location_assignment PIN_P6 -to bWM_PIO7 -set_location_assignment PIN_N5 -to bWM_PIO8 -set_location_assignment PIN_T4 -to bWM_PIO16 -set_location_assignment PIN_R4 -to bWM_PIO17 -set_location_assignment PIN_T5 -to bWM_PIO18 -set_location_assignment PIN_R6 -to bWM_PIO21 -set_location_assignment PIN_R5 -to bWM_PIO20 -set_location_assignment PIN_T7 -to bWM_PIO24 -set_location_assignment PIN_R7 -to bWM_PIO25 -set_location_assignment PIN_N9 -to bWM_PIO27 -set_location_assignment PIN_N11 -to bWM_PIO28 -set_location_assignment PIN_T10 -to bWM_PIO29 -set_location_assignment PIN_T4 -to bWM_PIO31 -set_location_assignment PIN_M6 -to bWM_PIO34 -set_location_assignment PIN_R4 -to bWM_PIO35 -set_instance_assignment -name IO_STANDARD "2.5 V" -to bWM_PIO36 -set_location_assignment PIN_N1 -to bWM_PIO36 -set_location_assignment PIN_E15 -to iWM_TX -set_location_assignment PIN_T6 -to oWM_RX -set_location_assignment PIN_R5 -to iWM_RTS -set_location_assignment PIN_R6 -to iWM_CTS -set_instance_assignment -name IO_STANDARD "2.5 V" -to oWM_RESET -set_location_assignment PIN_R1 -to oWM_RESET -set_instance_assignment -name IO_STANDARD LVDS -to oHDMI_TX* -set_instance_assignment -name IO_STANDARD LVDS -to oHDMI_CLK -set_location_assignment PIN_R16 -to oHDMI_TX[0] -set_location_assignment PIN_K15 -to oHDMI_TX[1] -set_location_assignment PIN_J15 -to oHDMI_TX[2] -set_location_assignment PIN_P16 -to "oHDMI_TX[0](n)" -set_location_assignment PIN_K16 -to "oHDMI_TX[1](n)" -set_location_assignment PIN_J16 -to "oHDMI_TX[2](n)" -set_location_assignment PIN_N15 -to oHDMI_CLK -set_location_assignment PIN_N16 -to "oHDMI_CLK(n)" -set_instance_assignment -name IO_STANDARD "2.5 V" -to bHDMI_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to bHDMI_SDA -set_location_assignment PIN_K5 -to bHDMI_SCL -set_location_assignment PIN_L4 -to bHDMI_SDA -set_location_assignment PIN_M16 -to iHDMI_HPD -set_instance_assignment -name FAST_INPUT_REGISTER ON -to iMIPI_D* -set_instance_assignment -name IO_STANDARD LVDS -to iMIPI_D* -set_instance_assignment -name IO_STANDARD LVDS -to iMIPI_CLK* -set_location_assignment PIN_L2 -to iMIPI_D[0] -set_location_assignment PIN_J2 -to iMIPI_D[1] -set_location_assignment PIN_L1 -to "iMIPI_D[0](n)" -set_location_assignment PIN_J1 -to "iMIPI_D[1](n)" -set_location_assignment PIN_M2 -to iMIPI_CLK -set_location_assignment PIN_M1 -to "iMIPI_CLK(n)" -set_location_assignment PIN_P2 -to bMIPI_SDA -set_instance_assignment -name IO_STANDARD "2.5 V" -to bMIPI_SDA -set_location_assignment PIN_P1 -to bMIPI_SCL -set_instance_assignment -name IO_STANDARD "2.5 V" -to bMIPI_SCL -set_location_assignment PIN_M7 -to bMIPI_GP[0] -set_location_assignment PIN_P9 -to bMIPI_GP[1] -set_instance_assignment -name IO_STANDARD "2.5 V" -to panel_en -set_location_assignment PIN_L4 -to panel_en -set_location_assignment PIN_C1 -to oFLASH_MOSI -set_location_assignment PIN_H2 -to iFLASH_MISO -set_location_assignment PIN_H1 -to oFLASH_SCK -set_location_assignment PIN_D2 -to oFLASH_CS -set_location_assignment PIN_R7 -to oFLASH_HOLD -set_location_assignment PIN_T7 -to oFLASH_WP -set_location_assignment PIN_N2 -to oSAM_INT -set_location_assignment PIN_L16 -to iSAM_INT -set_instance_assignment -name IO_STANDARD "2.5 V" -to oSAM_INT -set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to iSAM_INT \ No newline at end of file diff --git a/fpga/src/strix.qws b/fpga/src/strix.qws deleted file mode 100644 index 63563b7..0000000 Binary files a/fpga/src/strix.qws and /dev/null differ