feat: add FPGA raw jitter capture design with SPI register interface
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13 changed files with 936 additions and 2 deletions
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@ -55,6 +55,31 @@ set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
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set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
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# Sources and constraints
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set_global_assignment -name VERILOG_FILE ../rtl/strix.v
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set_global_assignment -name VERILOG_FILE ../rtl/sys_pll.v
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set_global_assignment -name VERILOG_FILE ../rtl/strix_core.v
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set_global_assignment -name VERILOG_FILE ../rtl/entropy_gen.v
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set_global_assignment -name VERILOG_FILE ../rtl/ring_osc.v
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set_global_assignment -name VERILOG_FILE ../rtl/raw_capture.v
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set_global_assignment -name VERILOG_FILE ../rtl/spi_slave.v
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set_global_assignment -name SDC_FILE strix.sdc
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# Configuration settings matching Arduino's Vidor projects; the .ttf is the input for the
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# flash image embedded in the SAMD21 sketch.
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set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL"
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set_global_assignment -name USE_CONFIGURATION_DEVICE ON
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set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE EPCS16
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set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
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set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
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set_global_assignment -name CONFIGURATION_VCCIO_LEVEL AUTO
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set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION ON
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set_global_assignment -name GENERATE_TTF_FILE ON
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set_location_assignment PIN_E2 -to iCLK
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set_location_assignment PIN_E1 -to iRESETn
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set_location_assignment PIN_E10 -to oSDRAM_ADDR[11]
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