feat: add FPGA raw jitter capture design with SPI register interface

fpga/rtl/raw_capture.v

@@ -0,0 +1,67 @@
+// Captures one burst of sampled bits into block RAM for offline analysis. Keeps every
+// decimation-th sample of the selected source and packs them MSB first into bytes.
+module raw_capture #(
+    parameter ADDR_WIDTH = 15  // 2^15 bytes = 256 Kbit per burst
+) (
+    input  wire                  clk,
+    input  wire                  reset,
+    input  wire [3:0]            samples,
+    input  wire [1:0]            source,
+    input  wire [15:0]           decimation,  // 0 and 1 both mean every sample
+    input  wire                  start,
+    output reg                   busy,
+    output reg                   done,
+    input  wire [ADDR_WIDTH-1:0] read_addr,
+    output reg  [7:0]            read_data
+);
+
+    reg [7:0] buffer [0:(1 << ADDR_WIDTH) - 1];
+
+    reg [15:0]           sample_count;
+    reg [2:0]            bit_count;
+    reg [6:0]            partial_byte;
+    reg [ADDR_WIDTH-1:0] next_addr;
+    reg                  write_enable;
+    reg [ADDR_WIDTH-1:0] write_addr;
+    reg [7:0]            write_data;
+
+    wire keep_sample = (sample_count == 16'd0);
+    wire count_wraps = (decimation <= 16'd1) || (sample_count == decimation - 16'd1);
+    wire new_bit     = samples[source];
+
+    always @(posedge clk) begin
+        write_enable <= 1'b0;
+        if (reset) begin
+            busy <= 1'b0;
+            done <= 1'b0;
+        end else if (start) begin
+            busy         <= 1'b1;
+            done         <= 1'b0;
+            sample_count <= 16'd0;
+            bit_count    <= 3'd0;
+            next_addr    <= {ADDR_WIDTH{1'b0}};
+        end else if (busy) begin
+            sample_count <= count_wraps ? 16'd0 : sample_count + 16'd1;
+            if (keep_sample) begin
+                partial_byte <= {partial_byte[5:0], new_bit};
+                bit_count    <= bit_count + 3'd1;
+                if (bit_count == 3'd7) begin
+                    write_enable <= 1'b1;
+                    write_addr   <= next_addr;
+                    write_data   <= {partial_byte, new_bit};
+                    next_addr    <= next_addr + 1'b1;
+                    if (&next_addr) begin
+                        busy <= 1'b0;
+                        done <= 1'b1;
+                    end
+                end
+            end
+        end
+    end
+
+    always @(posedge clk) begin
+        if (write_enable) buffer[write_addr] <= write_data;
+        read_data <= buffer[read_addr];
+    end
+
+endmodule