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feat: add FPGA raw jitter capture design with SPI register interface

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randogoth 2026-10-25 12:25:25 +02:00
parent 3ee8a5c3db
commit 0332d8eb33
13 changed files with 936 additions and 2 deletions
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.gitignore vendored
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@ -17,3 +17,6 @@ fpga/**/simulation/
# Devbox
.devbox/
# Python virtualenv created by devbox
.venv/