48 lines
1.5 KiB
Coq
48 lines
1.5 KiB
Coq
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// Measures a ring frequency: an 8-bit prescaler clocked by the ring itself divides it by
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// 256, and its top bit's rising edges are counted in the clk domain over a gate of
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// 2^GATE_BITS clk cycles. frequency = count * 256 * f_clk / 2^GATE_BITS.
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module freq_counter #(
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parameter GATE_BITS = 24 // 2^24 cycles at 120 MHz = 140 ms
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) (
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input wire clk,
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input wire reset,
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input wire signal, // asynchronous signal to measure (used as a clock)
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input wire start,
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output reg busy,
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output reg valid,
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output reg [31:0] count
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);
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reg [7:0] prescaler = 8'd0;
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always @(posedge signal) prescaler <= prescaler + 8'd1;
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// The SDC file cuts timing from prescaler into this synchronizer.
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reg [2:0] divided_history;
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always @(posedge clk) divided_history <= {divided_history[1:0], prescaler[7]};
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wire divided_rising = (divided_history[2:1] == 2'b01);
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reg [GATE_BITS-1:0] gate;
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reg [31:0] edges;
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always @(posedge clk) begin
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if (reset) begin
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busy <= 1'b0;
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valid <= 1'b0;
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end else if (start) begin
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busy <= 1'b1;
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valid <= 1'b0;
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gate <= {GATE_BITS{1'b0}};
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edges <= 32'd0;
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end else if (busy) begin
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gate <= gate + 1'b1;
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if (divided_rising) edges <= edges + 32'd1;
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if (&gate) begin
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busy <= 1'b0;
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valid <= 1'b1;
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count <= edges + divided_rising;
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end
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end
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end
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endmodule
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