90 lines
3 KiB
Coq
90 lines
3 KiB
Coq
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// Byte stream of entropy for the SAMD21: bits from the selected channel (optionally through a
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// von Neumann extractor) are packed MSB first into bytes and queued in a FIFO. When the FIFO
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// is full, new bytes are dropped and counted; bits are never reused.
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//
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// Reading: `head` is the oldest byte, valid while `available`; `pop` removes it. A popped
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// byte's successor appears on `head` two cycles later. `level` and `available` are registered
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// and lag by a cycle, which only ever understates what can be read.
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module entropy_stream #(
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parameter ADDR_WIDTH = 12 // 4096-byte FIFO
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) (
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input wire clk,
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input wire reset,
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input wire flush,
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input wire bit_in,
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input wire valid,
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input wire von_neumann,
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input wire pop,
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output reg [7:0] head,
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output reg available,
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output reg [ADDR_WIDTH:0] level,
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output reg [15:0] dropped // bytes dropped since flush, saturating
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);
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// Von Neumann (01 -> 0, 10 -> 1)
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reg pair_first, have_first;
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wire vn_valid = von_neumann ? (valid && have_first && bit_in != pair_first) : valid;
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wire vn_bit = von_neumann ? pair_first : bit_in;
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always @(posedge clk) begin
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if (reset || flush || !von_neumann) begin
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have_first <= 1'b0;
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end else if (valid) begin
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have_first <= ~have_first;
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pair_first <= bit_in;
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end
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end
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// Packing
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reg [6:0] partial;
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reg [2:0] bit_count;
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reg byte_ready;
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reg [7:0] byte_out;
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always @(posedge clk) begin
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byte_ready <= 1'b0;
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if (reset || flush) begin
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bit_count <= 3'd0;
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end else if (vn_valid) begin
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partial <= {partial[5:0], vn_bit};
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bit_count <= bit_count + 3'd1;
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if (bit_count == 3'd7) begin
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byte_ready <= 1'b1;
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byte_out <= {partial, vn_bit};
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end
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end
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end
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// FIFO
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reg [7:0] buffer [0:(1 << ADDR_WIDTH) - 1];
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reg [ADDR_WIDTH:0] write_ptr, read_ptr;
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wire [ADDR_WIDTH:0] fill = write_ptr - read_ptr;
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wire full = fill[ADDR_WIDTH];
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always @(posedge clk) begin
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if (reset || flush) begin
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write_ptr <= {(ADDR_WIDTH + 1){1'b0}};
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read_ptr <= {(ADDR_WIDTH + 1){1'b0}};
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dropped <= 16'd0;
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end else begin
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if (byte_ready) begin
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if (!full) begin
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buffer[write_ptr[ADDR_WIDTH-1:0]] <= byte_out;
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write_ptr <= write_ptr + 1'b1;
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end else if (dropped != 16'hFFFF) begin
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dropped <= dropped + 16'd1;
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end
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end
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if (pop && fill != 0) read_ptr <= read_ptr + 1'b1;
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end
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head <= buffer[read_ptr[ADDR_WIDTH-1:0]];
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level <= fill;
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available <= fill != 0 && !(pop && fill == 1);
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end
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endmodule
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