strix/devbox.json

{
  "$schema": "https://raw.githubusercontent.com/jetify-com/devbox/0.17.2/.schema/devbox.schema.json",
  "packages": [
    "arduino-cli@latest",
    "path:./nix#quartus",
    "iverilog@latest",
    "rustc@latest",
    "cargo@latest",
    "uv@latest"
  ],
  "shell": {
    "init_hook": [
      "echo 'Welcome to devbox!' > /dev/null"
    ],
    "scripts": {
      "setup": [
        "arduino-cli core update-index",
        "arduino-cli core install arduino:samd"
      ],
      "build": [
        "arduino-cli compile --fqbn arduino:samd:mkrvidor4000 --libraries arduino/libraries arduino/strix"
      ],
      "sim": [
        "mkdir -p /tmp/strix-sim",
        "iverilog -g2005 -DSIM -o /tmp/strix-sim/tb_strix_core fpga/sim/tb_strix_core.v fpga/rtl/strix_core.v fpga/rtl/entropy_generator.v fpga/rtl/health_monitor.v fpga/rtl/stats_block.v fpga/rtl/entropy_stream.v fpga/rtl/bias_amplifier.v fpga/rtl/amp_path.v fpga/rtl/amp_stage.v fpga/rtl/freq_counter.v fpga/rtl/ring_osc.v fpga/rtl/raw_capture.v fpga/rtl/spi_slave.v",
        "vvp -n /tmp/strix-sim/tb_strix_core",
        "iverilog -g2005 -o /tmp/strix-sim/tb_amp_stage fpga/sim/tb_amp_stage.v fpga/rtl/amp_stage.v",
        "vvp -n /tmp/strix-sim/tb_amp_stage"
      ],
      "fpga": [
        "cd fpga/src && quartus_sh --flow compile strix"
      ],
      "image": [
        "uv run tools/vidor_image.py fpga/src/output_files/strix.ttf arduino/libraries/StrixFPGA/src"
      ],
      "build-capture": [
        "arduino-cli compile --fqbn arduino:samd:mkrvidor4000 --libraries arduino/libraries arduino/strix_capture"
      ],
      "upload": [
        "arduino-cli upload --fqbn arduino:samd:mkrvidor4000 -p ${PORT:-/dev/ttyACM0} arduino/strix"
      ],
      "upload-capture": [
        "arduino-cli upload --fqbn arduino:samd:mkrvidor4000 -p ${PORT:-/dev/ttyACM0} arduino/strix_capture"
      ],
      "api-check": [
        "uv run tools/api_check.py --port ${PORT:-/dev/ttyACM0}"
      ],
      "onod-build": [
        "cargo build --release --manifest-path ${ONOD3000_DIR:-$HOME/Projects/randonautica/code/onod3000}/Cargo.toml --target-dir .build/onod3000"
      ],
      "jitter": [
        "uv run tools/jitter.py --port ${PORT:-/dev/ttyACM0} --out captures \"$@\""
      ]
    }
  }
}